Motorola Freescale Semiconductor M-Core MMC2001 Manuals

Manuals and User Guides for Motorola Freescale Semiconductor M-Core MMC2001. We have 1 Motorola Freescale Semiconductor M-Core MMC2001 manual available for free PDF download: Reference Manual

Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual (259 pages)

Brand: Motorola | Category: Microcontrollers | Size: 2.96 MB

Table of Contents
4
MMC2001 Block Diagram
21
Integer Cpu
22
M•CORE Overview
22
Features
23
Microarchitecture Summary
23
Programming Model
24
Programming Model
25
Data Format Summary
26
Data Organization in Memory
26
Data Organization in Registers
26
Operand Addressing Capabilities
27
Instruction Set Overview
27
M•CORE Instruction Set
27
M•CORE Bus Interface
29
Bus Characteristics
29
Bus Signals
30
Signal Relationships to Clocks
30
Signal Descriptions
31
M•CORE Bus Signals
31
Bus Operation
32
M•CORE Bus Signals
32
Interface Requirements for Read and Write Cycles
33
Processor Instruction/Data Transfers
34
External Multiplexer Connections
34
Bus Exception Cycles
35
Termination Result Summary
35
System Memory Map
36
Overview
36
Peripheral Module Address Allocation
36
MMC2001 Module Address Map
36
Peripheral Module Interface Operation
37
Peripheral Module Address Assignment
37
MMC2001 Address Map
37
Signal Descriptions
38
Overview
38
Functional Signal Groups
38
Signal Index
39
Pin Requirements in 144-Pin Package
39
Bus Signals
41
Address Bus (ADDR[19:0])
41
Data Bus (DATA[15:0])
41
Output Enable (OE)
41
Read/Write Enable (R/W)
41
Enable Byte 1 (EB1)
41
Enable Byte 0 (EB0)
41
Chip Selects (CS3, CS[2:0])
41
Internal ROM Disable (MOD)
41
Exception Control Signals
41
Low Voltage Reset (LVRSTIN)
42
Reset out (RSTOUT)
42
Clock Signals
42
Crystal Oscillator (XOSC, EXOSC)
42
Clock Input (CLKIN)
42
Clock Output (CLKOUT)
42
Debug and Emulation Support Signals
42
Test Clock (TCK)
42
Test Data Input (TDI)
42
Test Data Output (TDO)
43
Test Mode Select (TMS)
43
Test Reset (TRST)
43
Debug Event (DE)
43
Factory Test Mode (TEST)
43
External Interrupts/Gpio Signals
43
External Interrupts 7 - 0 (INT[7:0])
43
Keypad Signals
44
Column Strobes (COL[7:0])
44
Row Senses (ROW[7:0])
44
UART Module Signals
44
Receive Data (Rxd0, Rxd1)
44
Transmit Data (Txd0, Txd1)
44
Clear to Send (CTS0)
45
Request to Send (RTS0)
45
Serial Peripheral Interface Module Signals
45
SPI Data Master Out/Slave in (SPI_MOSI)
45
SPI Data Master In/Slave out (SPI_MISO)
45
SPI Serial Clock (SPI_CLK)
45
SPI Enable (SPI
45
SPI General-Purpose Output (SPI
45
Pulse Width Modulator Signals
45
Pwm[5:0]
46
Power and Ground Pins
46
Positive Supply (VDD )
46
Ground (GND)
46
Standby Battery Power (VBATT )
46
Standby Power Filter (VSTBY )
46
Rom Module
48
Overview
48
Functional Description
48
ROM Module Address Map
48
Applications
49
Static Ram Module
50
Overview
50
Functional Description
50
Static RAM Module Address Map
50
External Interface Module
52
Overview
52
Signals
52
Address Bus
52
EIM Block Diagram
52
Data Bus
53
Read/Write
53
Control Signals
53
Boot Mode
53
Chip Select Outputs
53
Chip-Select Address Range
54
Chip Select Address Range
54
EIM Interface Example
54
EIM Functionality
55
Configurable Bus Sizing
55
EIM Interface to Memory and Peripherals
55
Interface Requirements for Read and Write Cycles
56
External Boot ROM Control
57
Programmable Output Generation
57
Bus Watchdog Operation
57
Error Conditions
57
Show Cycles
58
EIM Programming Model
58
Chip-Select Control Registers
58
CS0 Control Register
58
EIM Memory Map
58
CS1, CS2, CS3 Control Registers
59
Wait State Control Field Settings
60
Data Port Size Field Settings
61
EIM Configuration Register
62
External Bus Timing Diagrams
64
Show Cycle Enable Field Settings
64
Write Memory Access (CSA = 0, WSC = 1, WWS = 0)
66
Clock Module and Low-Power Modes
74
Overview
74
CPU Core and Peripherals Clock Source
74
MMC2001 Clock Module
76
Low-Power Modes
77
CPU Core Low-Power Modes
77
Peripheral Behavior in Low-Power Modes
78
General Low-Power Features
80
CPU Core and Peripherals in Low-Power Modes
80
Timer/Reset Module
82
Overview
82
Timer/Reset Programming Model
82
Timer/Reset Module Address Map
82
Reset Operation
83
Reset Pins
83
Reset Sources
83
Reset Functional Block Diagram
83
Reset Sequence
84
Reset Source/Chip Configuration Register (RSCR)
84
Reset Source Register
84
Time-Of-Day Timer
85
TOD Block Diagram
85
TOD Operation
86
TOD in Low-Power Modes
86
Time-Of-Day Control/Status Register (TODCSR)
86
TOD Control/Status Register
86
TOD Seconds Register (TODSR)
87
TOD Fraction Register (TODFR)
87
TOD Seconds Register
87
TOD Seconds Alarm Register (TODSAR)
88
TOD Fraction Alarm Register (TODFAR)
88
TOD Fraction Register
88
TOD Seconds Alarm Register
88
Watchdog Timer
89
TOD Fraction Alarm Register
89
Watchdog Timer Block Diagram
89
Watchdog Timing Specifications
90
Watchdog Timer after Reset
90
Watchdog Timer Service Operation
90
Watchdog Timer in Wait Mode
90
Watchdog Timer in Doze Mode
90
Watchdog Timer in Stop Mode
90
Watchdog Timer in Debug Mode
91
Watchdog Timer Programming Model
91
Watchdog Control Register
91
Interval Timer (PIT)
92
Watchdog Service Register
92
PIT Operation
93
PIT as a "Set-And-Forget" Timer
93
PIT as a "Free-Running" Timer
94
Interval Timer Registers
94
Counter Reloading from the Modulus Latch
94
Counter in Free-Running Mode
94
PIT Control/Status Register (ITCSR)
95
PIT Control and Status Register
95
PIT Data Register (ITDR)
96
PIT Data Register
96
PIT Alternate Data Register (ITADR)
97
PIT in Low-Power Modes
97
PIT in Debug Mode
97
PIT Alternate Data Register
97
Interrupt Controller
98
Overview
98
Interrupt Controller Programming Model
99
Interrupt Source Register (INTSRC)
99
Interrupt Source Register
99
Interrupt Controller Address Map
99
Normal Interrupt Enable Register (NIER)
100
Fast Interrupt Enable Register (FIER)
100
Normal Interrupt Enable Register
100
Fast Interrupt Enable Register
100
Normal Interrupt Pending Register (NIPND)
101
Normal Interrupt Pending Register
101
Fast Interrupt Pending Register (FIPND)
102
Interrupt Request Input Assignments
102
Fast Interrupt Pending Register
102
Interrupt Source Assignment
103
Universal Asynchronous Receiver/Transmitter Module
104
Overview
104
UART Signals
105
RTS - Request to Send (UART0)
105
CTS - Clear to Send (UART0)
105
TXD - UART Transmit
106
RXD - UART Receive
106
Sub-Block Description
106
Transmitter
106
Receiver
106
Infrared Interface
107
Bit Clock Generator
107
General UART Definitions
107
UART Programming Model
108
UART Module Address Map
109
UART Receive Register (URX)
110
UART Receive Register
110
UART Transmitter Register (UTX)
111
UART Control Register 1 (UCR1)
112
UART Transmitter Register
112
UART Control Register 1
112
Txfl Field Settings
112
Rxfl Field Settings
113
UART Control Register 2 (UCR2)
114
UART Control Register 2
114
UART BRG Register (UBRGR)
116
UART BRG Register
116
UART Status Register (USR)
117
UART Status Register
117
UART Test Register (UTS)
118
UART Test Register
118
GPIO Pins and Registers
119
UART Port Control Register (UPCR)
119
UART Data Direction Register (UDDR)
119
UART Port Control Register
119
UART Data Direction Register
119
UART Port Data Register (UPDR)
120
Data Sampling Technique on the Receiver
120
UART Port Data Register
120
Start Bit - Ideal Case
122
Start Bit - Noise Case One
123
Start Bit - Noise Case Two
124
Start Bit - Noise Case Three
125
UART Operation in Low-Power System Modes
126
Start Bit - Noise Case Four
126
UART Low-Power Mode Operation
126
UART Operation in System Debug Mode
127
Interval Mode Serial Peripheral Interface
128
Overview
128
Operation
128
Interval (Master) Mode
130
Slave Mode
130
Signal Descriptions
130
SPI_MISO (Master In, Slave Out)
130
SPI_MOSI (Master Out, Slave In)
131
ISPI Programming Model
131
ISPI Data Register
132
ISPI Control Register
132
CLOCK COUNT Field Settings
134
ISPI Interval Control Register
135
ISPI Status Register
135
ISPI Programming Examples
136
Manual Mode Example
136
Slave Mode Example
137
Interval Model Example
137
ISPI Operation in Low-Power System Modes
138
ISPI Operation in System Debug Mode
138
ISPI Low-Power Mode Operation
138
External Interrupts/Gpio (Edge Port)
140
Overview
140
Interrupt/General-Purpose I/O Pin Descriptions (INT[0:7])
140
External Interrupt/Gpio Block Diagram
140
Edge Port Programming Model
141
Edge Port Pin Assignment Register (EPPAR)
141
Edge Port Pin Assignment Register
141
GPIO Edge Port Address Map
141
Edge Port Data Direction Register (EPDDR)
142
Edge Port Data Register (EPDR)
142
Edge Port Data Direction Register
142
Edge Port Data Register
142
Eppax Field Settings
142
Edge Port Flag Register (EPFR)
143
Edge Port Flag Register
143
Keypad Port
144
Overview
144
KPP Pin Description
145
Input Pins
145
Output Pins
145
KPP Programming Model
145
Keypad Control Register (KPCR)
145
Keypad Port Address Map
145
Keypad Status Register (KPSR)
146
Keypad Control Register
146
Keypad Status Register
147
Keypad Data Direction Register (KDDR)
148
Keypad Data Register (KPDR)
148
Keypad Data Direction Register
148
Keypad Data Register
148
Keypad Operation
149
Keypad Matrix Construction
149
Keypad Port Configuration
149
Keypad Matrix Scanning
149
Keypad Standby
150
Glitch Suppression on Keypad Inputs
150
Multiple Key Closures
151
Typical Keypad Configuration and Scanning Sequence
152
Pulse Width Modulator
154
Overview
154
PWM Programming Model
155
PWM Prescaler
155
PWM Address Map
156
PWM Control Register
157
PWM Control Registers
157
PWM Period Register
159
PWM Period Registers
159
CLK SEL Field Settings
159
PWM Width Register
160
PWM Counter Register
160
PWM Width Registers
160
PWM Count Registers
160
PWM Operating Range
161
PWM Operation in Low-Power System Modes
161
PWM Range at 16 Mhz
161
PWM Low-Power Mode Operation
161
Once™ DEBUG MODULE
162
Overview
162
Operation
162
Once Controller
163
Once Pins
164
Debug Serial Input (TDI)
164
Debug Serial Clock (TCK)
164
Debug Serial Output (TDO)
164
Debug Mode Select (TMS)
164
Test Reset (TRST)
165
Debug Event (DE)
165
Once Controller and Serial Interface
165
Once Interface Signals
166
Internal Debug Request Input (IDR)
166
CPU Debug Request (DBGRQ)
166
CPU Debug Acknowledge (DBGACK)
166
CPU Breakpoint Request (BRKRQ)
166
CPU Address, Attributes (ADDR, ATTR)
166
CPU Status (PSTAT)
166
Once Debug Output (DEBUG)
167
Once Controller Registers
167
Once Command Register (OCMR)
167
Once Control Register (OCR)
167
Once Status Register (OSR)
167
Once Command Register
168
Once Control Register
169
Once Register Addressing
169
Sequential Control Field Settings
170
Memory Breakpoint Control Field Settings
171
Once Status Register
172
Once Decoder (ODEC)
173
Memory Breakpoint Logic
173
Processor Mode Field Settings
173
Memory Address Latch (MAL)
174
Once Memory Breakpoint Logic
174
Breakpoint Address Base Registers (BABA, BABB)
175
Breakpoint Address Mask Registers (BAMA, BAMB)
175
Breakpoint Address Comparators
175
Memory Breakpoint Counters (MBCA, MBCB)
175
Once Trace Logic
175
Trace Counter (OTC)
176
Trace Operation
176
Once Trace Logic Block Diagram
176
Methods of Entering Debug Mode
177
Debug Request During RESET
177
Debug Request During Normal Activity
177
Debug Request During Stop, Doze, or Wait Mode
177
Software Request During Normal Activity
177
Enabling Once Trace Mode
177
Enabling Once Memory Breakpoints
178
Pipeline Information and Write-Back Bus Register
178
Program Counter Register (PC)
179
Instruction Register (IR)
179
Control State Register (CTL)
179
Control State Register
179
Write-Back Bus Register (WBBR)
180
Processor Status Register (PSR)
180
Instruction Address FIFO Buffer (PC FIFO)
181
Once PC FIFO
181
Reserved Test Control Registers (Reserved, MEM_BIST, FTCR, LSRL)
182
Serial Protocol Description
182
Once Commands
182
Target Site Debug System Requirements
182
Interface Connector for Jtag/Once Serial Port
183
Appendix Aelectrical Characteristics
184
Maximum Ratings
184
DC Electrical Specifications
184
Clock Input Specifications
185
AC Electrical Specifications
185
Reset, MOD Timing Specifications
185
CLKIN Timing (for Square Wave Input
185
External Interrupt Timing Specifications
186
Reset Timing
186
MOD Timing
186
EIM Timing Specifications
187
External Interrupt Timing
187
EIM Read/Write Timing
188
ISPI Timing Specifications
189
SPI Slave Timing (PHA = 0
190
SPI Slave Timing (PHA = 1
190
SPI Manual/Interval Mode Timing (PHA = 0
191
SPI Manual/Interval Mode Timing (PHA = 1
191
Once Timing Specifications
192
Test Clock Input Timing
192
TRST Timing
192
Appendix Bpackaging and Pin Assignments
194
Overview
194
Appendix Cprogramming Reference
196
Peripheral Module Address Assignment
196
MMC2001 Address Map
196
Interrupt Controller Programming Model
197
Interrupt Source Register (INTSRC
197
Normal Interrupt Enable Register (NIER
197
Interrupt Source Register
197
Interrupt Controller Address Map
197
Fast Interrupt Enable Register (FIER
198
Normal Interrupt Enable Register
198
Fast Interrupt Enable Register
198
Normal Interrupt Pending Register (NIPND
199
Fast Interrupt Pending Register (FIPND
199
Normal Interrupt Pending Register
199
Fast Interrupt Pending Register
199
Timer/Reset Programming Model
200
Reset Source/Chip Configuration Register (RSCR
200
Timer/Reset Module Address Map
200
Reset Source Register
201
Time-Of-Day Control/Status Register (TODCSR
202
TOD Seconds Register (TODSR
202
TOD Control/Status Register
202
TOD Fraction Register (TODFR
203
TOD Seconds Alarm Register (TODSAR
203
TOD Seconds Register
203
TOD Fraction Register
203
TOD Fraction Alarm Register (TODFAR
204
Watchdog Control Register (WCR
204
TOD Seconds Alarm Register
204
TOD Fraction Alarm Register
204
Watchdog Service Register (WSR
205
Watchdog Control Register
205
PIT Control/Status Register (ITCSR
206
Watchdog Service Register
206
PIT Control and Status Register
206
PIT Data Register (ITDR
207
PIT Alternate Data Register (ITADR
208
KPP Programming Model
208
PIT Data Register
208
PIT Alternate Data Register
208
Keypad Port Address Map
208
Keypad Control Register (KPCR
209
Keypad Status Register (KPSR
209
Keypad Control Register
209
Keypad Status Register
209
Keypad Data Direction Register (KDDR
210
Keypad Data Register (KPDR
210
Keypad Data Direction Register
210
EIM Programming Model
211
Chip-Select Control Registers
211
Keypad Data Register
211
EIM Address Map
211
CS0 Control Register
212
CS1, CS2, CS3 Control Registers
212
Wait State Control Field Settings
213
Data Port Size Field Settings
214
EIM Configuration Register
215
Chip-Select Address Range
215
EIM Configuration Register
216
PWM Module
217
Show Cycle Enable Field Settings
217
PWM Address Map
217
PWM Control Register
218
PWM Control Registers
218
PWM Period Register
220
PWM Width Register
221
PWM Period Registers
221
PWM Width Registers
221
PWM Counter Register
222
Edge Port Programming Model
222
Edge Port Pin Assignment Register (EPPAR
222
PWM Count Registers
222
GPIO Edge Port Address Map
222
Edge Port Data Direction Register (EPDDR
223
Edge Port Pin Assignment Register
223
Edge Port Data Direction Register
223
Eppax Field Settings
223
Edge Port Data Register (EPDR
224
Edge Port Flag Register (EPFR
224
Edge Port Data Register
224
Edge Port Flag Register
224
ISPI Programming Model
225
ISPI Send/Receive Data Register
225
ISPI Data Register
225
Interval Mode Serial Peripheral Interface Address Map
225
ISPI Control Register
226
ISPI Interval Control Register
228
ISPI Status Register
229
UART Programming Model
229
UART Module Address Map
230
UART Receive Register (URX
231
UART Receive Register
231
UART Transmit Register (UTX
232
UART Transmit Register
232
UART Control Register 1 (UCR1
233
UART Control Register 1
233
Txfl Field Settings
233
Rxfl Field Settings
234
UART Control Register 2 (UCR2
235
UART Control Register 2
235
UART BRG Register (UBRGR
237
UART Status Register (USR
237
UART BRG Register
237
UART Status Register
237
UART Test Register (UTSR
238
UART Port Control Register (UPCR
239
UART Test Register
239
UART Port Control Register
239
UART Data Direction Register (UDDR
240
UART Port Data Register (UPDR
240
UART Data Direction Register
240
UART Port Data Register
240
Once Registers
241
Once Command Register (OCMR
241
Once Command Register
241
Once Control Register (OCR
242
Once Control Register
242
Once Register Addressing
242
Sequential Control Field Definition
243
Memory Breakpoint Control Field Definition
244
Once Status Register (OSR
245
Once Status Register
245
Memory Address Latch (MAL
246
Breakpoint Address Base Registers (BABA, BABB
246
Breakpoint Address Mask Registers (BAMA, BAMB
246
Breakpoint Address Comparators
246
Memory Breakpoint Counters (MBCA, MBCB
246
Program Counter Register (PC
246
Processor Mode Field Definition
246
Instruction Register (IR
247
Control State Register (CTL
247
Control State Register
247
Write-Back Bus Register (WBBR
248
Processor Status Register (PSR
248
Reserved Test Control Registers (Reserved, MEM_BIST, FTCR, LSRL
248
Record of Changes
258

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Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual (259 pages)

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