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12.2.2 Interval (Master) Mode
Interval mode provides the user with the ability to exchange data at programmed peri-
odic intervals. This rate is controlled by three counters: the bit counter, the baud
counter, and the ISPI interval timer. This mode begins operation as soon as the
IVL_EN bit is set in the ISPI control register. (If a transfer is in progress, then opera-
tion begins upon completion of the existing transfer.) In interval mode (in contrast to
manual mode), the SPI_EN pin is active only when a transfer is in progress; that is, in
interval mode the state machine controls the enable pin. The SPI_EN enable bit (bit
12) must still be set in the ISPI control register.
An interval begins with the loading of the actual ISPI interval timer. Once this decre-
menting counter reaches zero, the state machine begins the data transfer. When the
transfer is completed, an interrupt is generated (if enabled by IRQ_EN), and the inter-
val is completed. At this point the ISPI automatically begins another interval by
reloading the interval timer. The length of an interval is governed by the following
equation:
Time_of_Interval = (HI_REFCLK_Period * 2 * (Interval_Count+2)) +
12.2.3 Slave Mode
In slave mode, data exchanges are controlled by external devices through the pins
SPI_CLK and SPI_EN. If pin SPI_EN is enabled (low), then data is latched into the
shift register on every other edge of SPI_CLK; the latching edge is determined by the
POL and PHA bits in the ISPI control register. Data is transferred from the shift regis-
ter to the ISPI (Rx) data register when pin SPI_EN becomes inactive, or when the bit
counter times out. In addition, IRQ is set at that time (if permitted by IRQ_EN). If the
RX data register is not unloaded prior to a new reload, the OVR (ISPI overrun) bit is
set in the ISPI status register, and the data is overwritten, causing prior received data
to be lost.
SPI_CLK must not exceed HI_REFCLK/16.
12.3 Signal Descriptions
12.3.1 SPI_MISO (Master In, Slave Out)
In either master mode, this pin is the input to the shift register. A new bit is shifted in
on each leading edge of SPI_CLK in normal clock mode or on each trailing edge of
SPI_CLK in inverted clock mode. In slave mode, this pin is the output of the shift reg-
ister. A new data bit is presented on each trailing edge of the SPI_CLK in normal
clock mode (PHA=0). As a slave mode output, SPI_MISO is three-stated when the
SPI_EN input is negated.
MMC2001
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
(HI_REFCLK_Period * Baud_Count * (Clock_Count+1))
INTERVAL MODE SERIAL PERIPHERAL INTERFACE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12-3
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