Cs0 Control Register; Cs1, Cs2, Cs3 Control Registers - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

CS0CR — CS0 Control Register
31 30 29 28
R 0 0 0 0
W
RESET:
15 14 13 12
R
WSC
W
RESET:
1 1 1 1
CS1CR — CS1 Control Register
CS2CR — CS2 Control Register
CS3CR — CS3 Control Register
31 30 29 28
R 0 0 0 0
W
RESET:
15 14 13 12
R
WSC
W
RESET:
X X X X
X = Undefined
* PA reset value equals zero for CS3 and one for CS[1:2]
Figure C-22 CS1, CS2, CS3 Control Registers
WSC — Wait-State Control
These four bits program the number of wait states for an access to the external device
connected to the chip select. Table C-6 shows the encoding of this field. When WWS
is cleared, setting WSC=0000 results in 1-clock transfers, WSC=0001 results in 2-
clock transfers, and WSC=1111 results in 16-clock transfers. When WSC=0000, the
WEN and CSA bits are ignored.
Set WSC=0000 and WWS=0 for access to fast SRAM devices (one-clock read and
write access), CSA=0, WSC=0001 and WWS=0 for access to normal SRAM (two-
clock read and write access), CSA=0, WSC=0001 and WWS=1 for access to Flash
memory (two-clock read access and three-clock write access), EDC, CSA and WSC
to the appropriate number for access to an LCD controller.
MMC2001
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27 26 25 24
0 0 0 0
11 10 9 8
WWS EDC CSA OEA
1 0 0 0
Figure C-21 CS0 Control Register
27 26 25 24
0 0 0 0
11 10 9 8
WWS EDC CSA OEA
X X X X
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23 22 21 20
0 0 0 0
7 6 5 4
WEN EBC DSZ
0 1 1 0
23 22 21 20
0 0 0 0
7 6 5 4
WEN EBC DSZ
X X X X
10004000
19 18 17 16
0 0 0 0
3 2 1 0
0
SP WP CSEN
0 0 1
10004004
10004008
1000400C
19 18 17 16
0 0 0 0
3 2 1 0
SP WP PA CSEN
X X 0/1* 0
MOTOROLA
C-17