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Service Manual
applied to the Analog Mod. Input of the syn-
thesizer circuit
Digital TX Audio Processing
The analog voice signal coming in through
the microphone is taken by the CODEC and
digitized. The samples are transmitted to the
DSP where microphone compensation and
echo cancellation processes take place. The
DSP uses ACELP to compress the samples
into data bits.These bits are interleaved with
speech data from adjacent speech frames for
error protection. System messages are then
combined with the data bits and sent to the
data converter for modulation. The data con-
verter modulates the data using differential
quadrature phase shift keying (DQPSK). The
bit streams generated from this step are con-
verted to analog signals which are filtered
before being transmitted.
DSP Lucent 1629
Digital Signal Processor, 80 MIPS, 3 volt op-
eration. It has a DPS1600 core with 16k
words of internal dual-port RAM and 48k
words of ROM. It is contained in a 169 ball
µBGA package with the balls on a 13 x 13mm
grid on 0.8mm centers.
Stuart IC
The STUART chip is a device intended for
the following five functions.
The HPI module provides a bus intercon-
•
nection function, the host port, for the call
processor (HC12) to talk to the DSP section
via the call processor' s parallel bus, intercon-
nected to the DSP' s parallel memory bus.
The DSP Timer module provides a timer
•
function controlled from DSP.
The IO, test, 19.44MHz clock control, SPI,
•
and CS switch module provides a 4-bits gen-
eral-purpose I/O port, with programmable
data direction, chip testing output pins
muxed with IO pins, 19.44MHz clock control,
SPI bus enable control, and special RAM chip
select switch function. It also is used to gen-
erate a PWM output (PWM_OSC pin).
The GP timer module is a general purpose
•
timer. It is synchronous, 16 bits, count-down,
preloadable, readable, and reloading on ter-
minal count. It' s input clock is 32.768KHz,
which can be disabled, divided-by-2, or di-
vided-by-4.
The FIFO SOI Interface provides a 96 bit
•
and a 16 bit buffer register accessible by ei-
ther the DSP or HC12. The DSP controls who
has write access to the data buffer and the
SPI control register. Data is written in using
8 bit words and sent via the RF SPI as either
a 96 bit or 16 bit write. The SPI clock speed
is selectable as either 4.86MHz or 1.215MHz.
The external SPI clock automatically stops
after each write. The internal SPI clock can
be disabled to save current. A maskable in-
terrupts are available at the end of each SPI
write.
GCAP II
GCAP II is intended to provide audio and
power management functions for Motorola
cellular telephone applications. GCAP II is
composed of two die. The GCAP II contains
the following functions:
2.775V linear regulator (V1)
•
5V linear regulator (VSIM)
•
2.775V linear regulator (V2)
•
2.775V linear regulator (V3)
•
Motorola Confidential Proprietary
General Description
GCAP II
69
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