Memory Maps; Processor Memory Map; Default Processor Memory Map - Motorola MVME2603-1121A Installation And Use Manual

Memory Maps

There are three points of view for memory maps:
The following sections give a general description of the
MVME2603/2604 memory organization from the above three
points of view. Detailed memory maps can be found in the
MVME2600 Series Single Board Computer ProgrammerÕs Reference
Guide (part number V2600A/PG).

Processor Memory Map

The processor memory map configuration is under the control of
the Raven bridge controller ASIC and the Falcon memory controller
chip set. The Raven and Falcon devices adjust system mapping to
suit a given application via programmable map decoder registers.
At system power-up or reset, a default processor memory map
takes over.

Default Processor Memory Map

The default processor memory map that is valid at power-up or
reset remains in effect until reprogrammed for specific
applications. Table 2-1 defines the entire default map ($00000000 to
$FFFFFFFF). Table 2-2 further defines the map for the local I/O
devices (accessible through the PCI/ISA I/O Space).
The mapping of all resources as viewed by the processor
(MPU bus memory map)
The mapping of onboard resources as viewed by PCI local
bus masters (PCI bus memory map)
The mapping of onboard resources as viewed by VMEbus
masters (VMEbus memory map)
Operating Instructions
2-5
2