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5 . 2 . 3
CPU
(80C85)
Operation Test
X I
VDD
X
2
2
RESET OUT
3
SOD
4
SI D
5
TRAP
6
RST7.5
7
RST6.5
8
RST5.5
9
INTR
10
-
INTA
11
ADO
12
AD1
13
AD2
14
AD3
15
A D4
16
AD5
17
AD6
18
AD7
19
GND
20
HOLD
HLDA
CLK
RESET
READY
101M
S1
-
R D
-
WR
ALE
S O
A1 5
A14
A1 3
A1
2
A1 1
A10
A9
A8
Figure 5.2 80C85 Terminal Connection (Top view)
(1) 80C85 Terminal Signals
When turning on the PC-8301 power siipply or depressing the reset switch. if each
terminal of U17 (80C85) operates correctly, you can confirm the p~llse changing to
the opposite level at each terminal.
Following signals are like next.
RESET
(P36) "13" level
(+5 V)
RESET OUT (P3)
"L"
level
(+O V)
I-I LDA
(P38)
"L"
level
(+O V)
TRAP
(P6)
"L" level
(+O V)
VDD (+5 V)
(P40) "H" level
(+5 V)
G N D
(P20) "L" level
(+0 V)
Thcn the contents of Figure 5.3 arc displdyed on the monitor.
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