Table of Contents
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Table of Contents
Related Manuals for Philips PDIUSBD12
Summary of Contents for Philips PDIUSBD12
- Page 1 Philips Semiconductors Interconnectivity 1 September 1998 PDIUSBD12 Evaluation Board (PC Kit) User’s Manual Rev. 2.1 _______________________________________________________________________________________________ Philips Semiconductors - Asia Product Innovation Centre Visit http://www.flexiusb.com...
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Page 2: Disclaimer
PDIUSBD12 Evaluation Board (PC Kit) User’s Manual Rev. 2.1 This is a legal agreement between you (either an individual or an entity) and Philips Semiconductors. By accepting this product, you indicate your agreement to the disclaimer specified as follows: DISCLAIMER PRODUCT IS DEEMED ACCEPTED BY RECIPIENT. -
Page 3: Table Of Contents
System Requirements............................. 4 Installation..............................5 Jumper’s setting on PDIUSBD12 ISA bridging board ................... 5 Location of key components on the PDIUSBD12 evaluation board............... 6 Installation of firmware, INF and driver......................7 Using the Host Applet ............................ 7 HARDWARE DESCRIPTION..................9 Block Diagram.............................. -
Page 4: Installation Of Pdiusbd12 Evaluation Board
INSTALLATION OF PDIUSBD12 EVALUATION BOARD Introduction The PDIUSBD12 evaluation kit uses 2 PC as a complete USB development environment, a host PC with USB host capability and a device PC running PDIUSBD12’s firmware. The PDIUSBD12 ISA bridging board is plugged inside the device PC and connects to the evaluation board using a 25-wire cable. -
Page 5: Installation
Jumper’s setting on PDIUSBD12 ISA bridging board The PDIUSBD12 ISA bridging board is plugged inside the device PC. It will occupy I/O, IRQ and DMA resources of the device PC. To avoid possible conflicts in settings, we suggest removal of all the unnecessary cards from the device PC. -
Page 6: Location Of Key Components On The Pdiusbd12 Evaluation Board
DMA by default. If this kind of sound card is installed, you should check its settings or remove it. DMA3 No conflict. Location of key components on the PDIUSBD12 evaluation board. D5 D4 D3 D2 See the table below for the list of connectors. Connector... -
Page 7: Installation Of Firmware, Inf And Driver
USB Chapter 9 test programs. The operation of each endpoint is designed according to its nature that is supported in PDIUSBD12. Generic in and generic out endpoints has max packet size of 16 bytes and supports I/O access only. - Page 8 Main endpoints support 3 different test modes: 1. Scan mode: The PDIUSBD12 evaluation board acts like a scanner. It sends data packets to the host PC as fast as possible. This mode is used to evaluate the maximal Bulk In transfer rate.
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Page 9: Hardware Description
These input and output ports are designed for test purposes, such as test switches and test LEDs. They also act as glue logic to adapt the PDIUSBD12 to the ISA bus. For example, ISA interrupt is edge triggered, but PDIUSBD12 interrupt is level triggered. The MSB of the general output port is used as interrupt enable to convert level triggered interrupt to edge triggered. -
Page 10: Connectors
CLKOUT: This line is connected to PDIUSBD12 CLKOUT pin. DATA4 -AD_EN: This line is the decoder output for address decoding A3 to A9. This signal is active low when PDIUSBD12 evaluation board I/O address is selected. DATA3 RESET: This line is used to reset or initialize system logic upon power-up and is active high. -
Page 11: Pal Equations
Page 11 of 14 Interconnectivity PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1 DATA0 T/C, Terminal Count: This line provides a pulse when terminal count for any DMA channel is reached. This signal is active high. ADDR2 -DACK: This line is used to acknowledge DMA request and is active low. -
Page 12: Schematics
Page 12 of 14 Interconnectivity PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1 Schematics Schematics for PDIUSBD12 evaluation board V_BUS 4.7 TANT V_BUS Ferrite Bead BUS POWERED 4.7 TANT 470P, Ceramic VBUS GREEN DB25 PDIUSBD12 ADDR0 4.7K 4.7K DATA0... -
Page 13: Schematic For Pdiusbd12 Isa Bridging Board
Page 13 of 14 Interconnectivity PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1 Schematic for PDIUSBD12 ISA bridging board DB25 I/O CH CK DATA[0..7] RESET DATA7 DATA7 ZERO_WA IT DATA6 DATA6 IRQ2 DATA5 DATA5 DATA4 DATA4 -AD_EN DRQ2 DATA3... -
Page 14: Bill Of Materials
R4,R5 4.7K R7,R8,R9,R10 S1,S2,S3,S4 SW PUSHBUTTON BUS POWERED PDIUSBD12 74LS245 74HCT244 74LS05 16L8 74HCT273 6MHz Bill of materials of the PDIUSBD12 ISA bridging board Item Quantity Reference Part C1,C4,C5 C2,C3 4.7u JP1,JP2,JP3,JP4,JP5,JP6 JUMPER CON AT62 DB25 SW DIP-8 74HCT688 _______________________________________________________________________________________________...