Philips PDIUSBD12 Product Data
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Philips PDIUSBD12 Product Data

Philips PDIUSBD12 Product Data

Usb interface device with parallel bus
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1. Description

2. Features

PDIUSBD12
USB interface device with parallel bus
Rev. 08 — 20 December 2001
The PDIUSBD12 is a cost and feature optimized USB device. It is normally used in
microcontroller based systems and communicates with the system microcontroller
over the high-speed general purpose parallel interface. It also supports local DMA
transfer.
This modular approach to implementing a USB interface allows the designer to
choose the optimum system microcontroller from the available wide variety. This
flexibility cuts down the development time, risks, and costs by allowing the use of the
existing architecture and minimize firmware investments. This results in the fastest
way to develop the most cost effective USB peripheral solution.
The PDIUSBD12 fully conforms to the USB specification Rev. 2.0 (basic speed) . It is
also designed to be compliant with most device class specifications: Imaging Class,
Mass Storage Devices, Communication Devices, Printing Devices, and Human
Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like
Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers
an immediate cost reduction for applications that currently use SCSI
implementations.
The PDIUSBD12 low suspend power consumption along with the LazyClock output
allows for easy implementation of equipment that is compliant to the ACPI™,
OnNOW™, and USB power management requirements. The low operating power
allows the implementation of bus powered peripherals.
In addition, it also incorporates features like SoftConnect™, GoodLink™,
programmable clock output, low frequency crystal oscillator, and integration of
termination resistors. All of these features contribute to significant cost savings in the
system implementation and at the same time ease the implementation of advanced
USB functionality into the peripherals.
Complies with the Universal Serial Bus specification Rev. 2.0 (basic speed)
High performance USB interface device with integrated SIE, FIFO memory,
transceiver and voltage regulator
Compliant with most Device Class specifications
High-speed (2 Mbytes/s) parallel interface to any external microcontroller or
microprocessor
Fully autonomous DMA operation
Integrated 320 bytes of multi-configuration FIFO memory
Product data

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Summary of Contents for Philips PDIUSBD12

  • Page 1: Description

    Product data 1. Description The PDIUSBD12 is a cost and feature optimized USB device. It is normally used in microcontroller based systems and communicates with the system microcontroller over the high-speed general purpose parallel interface. It also supports local DMA transfer.

  • Page 2: Pinning Information

    Multiple interrupt modes to facilitate both bulk and isochronous transfers. 3. Pinning information 3.1 Pinning Fig 1. Pin configuration. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 2 of 35...

  • Page 3: Pin Description

    To operate the IC at 3.3 V, supply 3.3 V to both V and V OUT3.3 pins. D− USB D− data line. USB D+ data line. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 3 of 35...

  • Page 4: Ordering Information

    This is a conceptual block diagram and does not include each individual signal. Fig 2. Block diagram. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 4 of 35...

  • Page 5: Functional Description

    6.6 SoftConnect The connection to the USB is accomplished by bringing D+ (for high-speed USB device) HIGH through a 1.5 kΩ pull-up resistor. In the PDIUSBD12, the 1.5 kΩ pull-up resistor is integrated on-chip and is not connected to V by default.

  • Page 6: Goodlink

    PDIUSBD12. The multiplexed address and data bus of the 80C51 can now be connected directly to the data bus of the PDIUSBD12. The address phase will be ignored by the PDIUSBD12. The clock input signal of the 80C51 (pin XTAL1) can be provided by output CLKOUT of the PDIUSBD12.

  • Page 7: Dma Transfer

    After the DMA controller has been programmed, the DMA enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. The PDIUSBD12 can be programmed for single-cycle DMA or burst mode DMA. In single-cycle DMA, the DMREQ pin is deactivated for every single acknowledgement by the DMACK_N before being re-asserted.

  • Page 8: Endpoint Description

    DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N. The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines.
  • Page 9 This endpoint supports DMA access. Denotes double buffering. The size shown is for a single buffer. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001...

  • Page 10: Main Endpoint

    Read 1 byte Read Buffer Selected Endpoint Read n bytes Write Buffer Selected Endpoint Write n bytes 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 10 of 35...

  • Page 11: Command Description

    ADDRESS: The value written becomes the address. ENABLE: A ‘1’ enables this function. Fig 4. Set Address/Enable command: bit allocation. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 11 of 35...

  • Page 12: Set Endpoint Enable

    The second byte is the clock division factor byte. Table 5 for bit allocation. Fig 6. Set mode command, Configuration byte. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 12 of 35...
  • Page 13 SOF-ONLY INTERRUPT MODE SV00862 Table 6 for bit allocation. Fig 7. Set mode command, Clock division factor byte. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 13 of 35...

  • Page 14: Set Dma

    (status and byte length information) is not transferred to/from the local CPU. This allows DMA data to be continuous and not interleaved by chunks of these headers. For DMA read operations, the header will be skipped by the PDIUSBD12. See Section 11.3.5 “Read buffer”...

  • Page 15: Data Flow Commands

    DMA DIRECTION This bit determines the direction of data flow during a DMA transfer. A ‘1’ means external shared memory to PDIUSBD12 (DMA Write); a ‘0’ means PDIUSBD12 to the external shared memory (DMA Read). DMA ENABLE Writing a ‘1’ to this bit will start DMA operation through the assertion of pin DMREQ.
  • Page 16 Bit Symbol Description SUSPEND CHANGE When the PDIUSBD12 did not receive 3 SOFs, it will go into suspend state and the Suspend Change bit will be HIGH. Any change to the suspend or awake state will set this bit HIGH and generate an interrupt.

  • Page 17: Select Endpoint

    This command also resets the corresponding interrupt flag in the interrupt register, and clears the status, indicating that it was read. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 17 of 35...
  • Page 18 1001 Sent or received NAK 1010 Sent Stall, a token was received, but the endpoint was stalled 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 18 of 35...

  • Page 19: Read Buffer

    The first two bytes will be skipped in the DMA read operation. Thus, the first read will get Data byte 1, the second read will get Data byte 2, etc. The PDIUSBD12 can determine the last byte of this packet through the EOP termination of the USB packet.

  • Page 20: Clear Buffer

    Fig 14. Set endpoint status: bit allocation. 11.3.10 Acknowledge setup Code (Hex) — F1 Transaction — none 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 20 of 35...

  • Page 21: General Commands

    SOF. The frame number is returned Least Significant byte first. Fig 15. Read current frame number. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 21 of 35...

  • Page 22: Interrupt Modes

    DC output voltage −40 °C operating ambient Section 14 temperature in free air Section 15 per device. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 22 of 35...

  • Page 23: Static Characteristics

    SoftConnect = ON kΩ Includes external resistors of 18 Ω ± 1% on D+ and D−. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 23 of 35...

  • Page 24: Dynamic Characteristics

    DEOP RECEIVER EOP WIDTH: t EOPR1 EOPR2 SV00837 Fig 16. Differential data-to-EOP transition skew and EOP width. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 24 of 35...
  • Page 25 (EOT-1)byte. The t and t timings are valid for back-to-back data access only. Fig 17. ALE timing. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 25 of 35...
  • Page 26 RD_N (only) HIGH to next data valid RHNDV EOT timings − EOT_N LOW to DMREQ LOW time ELRL 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 26 of 35...
  • Page 27 SLRL DMACK_N t SHAH RD_N/WR_N SV00875 Fig 20. Burst DMA timing. Fig 21. DMA terminated by EOT. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 27 of 35...

  • Page 28: Test Information

    1.5kΩ IS INTERNAL TEST POINT 22Ω D. U. T. = 50pF 15kΩ SV00849 Fig 22. Load for D+/D−. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 28 of 35...

  • Page 29: Package Outline

    EUROPEAN ISSUE DATE VERSION PROJECTION JEDEC EIAJ 97-05-22 SOT136-1 075E06 MS-013 99-12-27 Fig 23. SO28 package outline. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 29 of 35...
  • Page 30 OUTLINE EUROPEAN ISSUE DATE VERSION PROJECTION JEDEC EIAJ 95-02-04 SOT361-1 MO-153 99-12-27 Fig 24. TSSOP28 package outline. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001 30 of 35...

  • Page 31: Soldering

    The footprint must incorporate solder thieves downstream and at the side corners. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001...

  • Page 32: Manual Soldering

    0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 9397 750 09238 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 08 — 20 December 2001...

  • Page 33: Revision History

    20011220 Product data; version 8. Supersedes PDIUSBD12_7 of 20011124 (9397 750 08969). Modifications: • Added new USB logo to indicate PDIUSBD12 as a USB-IF certified product. • Section 1 “Description” changed USB specification Rev. 1.1 to USB specification Rev. 2.0 (basic speed) .

  • Page 34: Data Sheet Status

    This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.

  • Page 35: Table Of Contents

    Bit clock recovery ..... . . 5 Philips Serial Interface Engine (PSIE) ..5 Definitions .

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