Camera Bus Timings - Honeywell IS4910 Integration Manual

Camera Bus Timings

The non-decode engine outputs pixel data via an 8-bit parallel data bus. The rate at which data is output is
determined by the pixel clock, which can be set for 48, 24, or 12 MHz. When the horizontal and vertical synch
signals are high, valid pixel data is latched on the rising edge of the PCLK. New pixel data is then driven on to
the bus on the falling edge. The VSYNC, HSYNC, and Pixel Data timings are relative to the PCLK and are
related as shown in the following timing diagram.
Symbol
f PCLK
PCLK frequency
t PCLKL
PCLK low width
t PCLKH
PCLK high width
t DV
PCLK to output valid
* © of STMicroelectronics – All rights reserved.
Figure 12. Parallel Data Output Video Timing*
Parallel Data Interface Timings*
Description
[1/2*1/fPCLK)] – 0.5
[1/2*1/fPCLK)] – 0.5
-0.1
Table 1. Parallel Data Interface Timings*
Min.
48
[1/2*1/fPCLK)] + 0.5
[1/2*1/fPCLK)] + 0.5
+2.5
Max.
MHz
ns
ns
ns
Unit
17