Retry Sequence - Motorola MC68340 User Manual

Integrated processor with dma
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S0
CLKOUT
A31–A0
FC3–FC0
R/W
AS
DS
DSACKx
D15–D0
BERR
HALT
The MC68340 retries any read or write cycle of a read-modify-write operation separately;
RMC remains asserted during the entire retry sequence. Asserting BR along with BERR
and HALT provides a relinquish and retry operation. The MC68340 does not relinquish the
bus during a read-modify-write operation. Any device that requires the MC68340 to give
up the bus and retry a bus cycle during a read-modify-write cycle must assert only BERR
and BR ( HALT must not be included). The bus error handler software should examine the
read-modify-write bit in the special status word (see Section 5 CPU32) and take the
appropriate action to resolve this type of fault when it occurs.
MOTOROLA
Freescale Semiconductor, Inc.
S2
SW
SW
S4
DATA
IGNORED
READ CYCLE WITH
RETRY
Figure 3-19. Retry Sequence
MC68340 USER'S MANUAL
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S0
S2
S4
HALT
READ RERUN
3- 37

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