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CHAPTER 2 CPU
2.7
Instruction Overview
The FR series supports logical operation, bit manipulation, and direct addressing
instructions, which are optimized for embedding applications, in addition to general
RISC instructions. Each instruction, which is 16 bits long (some are 32 bits or 48 bits
long), shows excellent memory use efficiency. See Appendix E, "Instructions," for
details about instructions.
The instruction set can be divided into the following function groups:
• Arithmetic operation
• Load and store
• Branch
• Logical operation and bit manipulation
• Direct addressing
• Others
Instruction Overview
Arithmetic operation
Arithmetic operation includes the standard arithmetic operation instructions (addition,
subtraction, and comparison) and shift instructions (logical shift and arithmetic shift).
addition and subtraction, operation with carry for multiword length operation, and operation
without changing the flag value, which is useful for address calculation, are also supported.
Furthermore, the "32 x 32 bits" and "16 x 16 bits" multiply instructions and "32/32 bits" step
divide instructions are available.
The FR series also supports immediate transfer instructions, which allow immediate data to be
set in registers, and inter-register transfer instructions.
Every arithmetic operation instruction executes using the general-purpose registers and
multiplication/division registers in the CPU.
Load and store
Load or store instructions are used to read data from external memory or write data to it. They
are also used to read data from the peripheral circuits (I/O) inside the chip or write data to it.
Load and store instructions each use three types of access data length: byte, half word, and
word. The FR series supports not only general register indirect memory addressing but also, for
some instructions, register indirect memory addressing with displacement or with register
increment/decrement.
Branch
The branch instruction group includes branch, call, interrupt, and recovery instructions. There
are two types of branch instructions. One has a delay slot and one does not. They can be used
most suitably for applications.
For more information on the branch instructions, see Sections 2.7.1, "Branch instructions with
delay slot," and 2.7.2, "Branch instructions without delay slot."
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