Chipset - Asus K8N-LR User Manual

MTRR Mapping [Continuous]
Sets the method used for programming CPU MTRRs when 4GB or more
memory is installed on the system. When set to Discrete, the BIOS leaves
the PCI hole below the 4GB boundary undescribed. Set to Continuous to
describe the PCI hole as non-cacheable.
Configuration options: [Continuous] [Discrete]
4.4.2

Chipset

The Chipset menu allows you to change the advanced chipset settings.
Select an item then press <Enter> to display the sub-menu.
NorthBridge Configuration
SouthBridge Configuration
NorthBridge Configuration
The NorthBridge Configuration menu allows you to change the Northbridge
settings.
NorthBridge Chipset Configuration
Memory Configuration
ECC Configuration
Power Down Control
Memory CLK
CAS Latency (Tcl)
RAS/CAS Delay (Trcd)
Min Active RAS (Tras)
Row Precharge Time (Trp)
RAS/RAS Delay (Trrd)
Row Cycle (Trc)
Row Refresh Cycle (Trfc)
Read Write Delay (Trwt)
Read Preamble
Asynchronous Latency
ASUS K8N-LR
[Auto]
: 200 MHz
: 3.0
: 3 CLK
: 8 CLK
: 3 CLK
: 2 CLK
: 11 CLK
: 14 CLK
: 4 CLK
: 5.5 ns
: 7 ns
Options for NB.
Select Screen
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
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