(73) General event register (GEV) Common register
The GEV register indicates the causes of the general event.
Register
Address
Name
GEV_RO
01A0 H
31
30
29
28
15
14
13
12
Bit
Field
Reserved
Reserved
D31-D2
TGE
D1
1: Indicates that the bits of the TGE register are set.
0: TGE register is all 0.
D0
DGE
1: Indicates that the bits of the DGE register are set.
0: DGE register is all 0.
(74) General event Mask register (GEV_M)
The GEV_M register is mask register of GEV register.
Register
Address
Name
GEV_M
01A4 H
31
30
29
28
15
14
13
12
Bit
Field
Reserved
Reserved
D31-D2
TGE
D1
1: mask
D0
DGE
1: mask
CHAPTER 5 REGISTERS
Access
Default
R
00000000 H
27
26
25
24
Reserved
11
10
9
8
Reserved
Common register
Access
Default
R/W
00000003 H
27
26
25
24
Reserved
11
10
9
8
Reserved
0: unmask
0: unmask
PRELIMINARY
Function
Read-only
23
22
21
20
7
6
5
4
Function
Function
Mask register
23
22
21
20
7
6
5
4
Function
NEC confidential and Proprietary
19
18
17
16
3
2
1
0
TGE
DGE
Default
0
0
0
19
18
17
16
3
2
1
0
TGE
DGE
Default
0
1
1
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