NEC UPD98413 User Manual page 153

Register
Transmit interrupt cause
register (ICT)
Transmit ATM/POS
interface error register
(APIET)
Receive interrupt cause
register (ICR)
Receive ATM/POS
interface error register
(APIER)
General-purpose input port
status register (GPIN)
General event Register
(GEV)
Register
Transmit ATM/POS layer
event detection register
(DAPET)
Receive section and line
layer event detection
registers (DSLER)
Receive section and line
layer event termination
registers (TSLER)
Receive pointer and path
layer event detection
registers (DPPER)
Receive pointer and path
layer event termination
registers (TPPER)
Receive ATM/POS layer
event detection registers
(DAPER)
Receive ATM/POS layer
event termination registers
(TAPER)
General event termination
register (DGE)
General event termination
register (TGE)
CHAPTER 4 INTERFACES
Table 4-8. Interrupt Cause Register
Outline
• This register indicates which detailed transmit cause register bit is set.
• When at least one bit in this register is set to 1, the bit of the corresponding port in the INT
register is set.
• The APIET register indicates the causes of a transmit ATM/POS interface error.
• When at least one bit in this register is set to 1, the APIET bit in the INT register is set.
• This register indicates which detailed receive cause register bit is set.
• When at least one bit in this register is set to 1, the bit of the corresponding port in the INT
register is set.
• The APIER register indicates the causes of a receive ATM/POS interface error.
• When at least one bit in this register is set to 1, the APIER bit in the INT register is set.
• The GPIN register indicates the signal label of each general-purpose input pin.
• When at least one bit in this register is set to 1, the GPIN bit in the INT register is set.
• The GEV register indicates cause of the General event.
• When at least one bit in this register is set to 1, the GEV bit in the INT register is set.
Table 4-9. Detailed Cause Register
Outline
• This register indicates whether the occurrence of event was detected.
• When at least one bit in the DAPET register is set to 1, the DAPET bit in the ICT register is
set.
• This register indicates that section and Line layer event has detected.
• When at least one bit in the DSLER register is set to 1, the DSLER bit in the ICR register is
set.
• This register indicates that section and Line layer event has terminated.
• When at least one bit in the TSLER register is set to 1, the TPPER bit in the ICR register is
set.
• This register indicates that pointer and path layer event has detected.
• When at least one bit in the DPPER register is set to 1, the DPPER bit in the ICR register
is set.
• This register indicates that pointer and path layer event has terminated.
• When at least one bit in the TPPER register is set to 1, the TPPER bit in the ICR register
is set.
• This register indicates that ATM/POS layer event has detected.
• When at least one bit in the DAPER register is set to 1, the DAPER bit in the ICR register
is set.
• This register indicates that ATM/POS layer event has terminated.
• When at least one bit in the TAPER register is set to 1, the TAPER bit in the ICR register
is set.
• This register indicates that general event has detected.
• When at least one bit in the DGE register is set to 1, the DGE bit in the GEV register is set.
• This register indicates that general event has terminated.
• When at least one bit in the TGE register is set to 1, the TGE bit in the GEV register is set.
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