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MODE REGISTER - CONT'D.
ETCCG
32
Margin Control.
Bit 32 shall be used to inform the Software
when it can control margins.
A One shall indicate that soft-
ware has control.
When the LOCAL/REMOTE switch on the power
supply is in REMOTE and Bit 35 = 1, Bit 32 shall be set to
a
one by occurrence of the following conditions:
the NORMAL/
TEST switch is in the TEST position,
the Memory and CU overlap
Inhibit switches are OFF, the Timing Margins for the OU, CU,
DU and VU are NORMAL, and the Forced Data and ZAC Parity are
OFF.
33
Hexadecimal Exponent Floating Point Arithmetic Mode can be
set.
When this bit is set, the Hex Mode will become effective
when the Indicator Register Bit 32 is set to a ONE.
34
UNUSED
35
Use Mode Register.
Unless Bit 35 = 1, all other bits in the
Mode Register will be ignored and the History Register will be
locked.
ETCCC
36-48
'13 MOST SIGNIFICANT ADDRESS BITS
(ON GCOS III, E0 — E5, A0 - A6).
49-50
Unassigned
51 CACHE
DIRECTORY PARITY BIT
52 CACHE
DIRECTORY LEVEL FULL/EMPTY
53
Unassigned
54 CACHE
CSHl ENABLED
ETCCG
55 CACHE
CSH2 ENABLED
56
57 CACHE
INSTRUCTIONS ENABLED TO CACHE
58
Unassigned
59 CACHE
CACHE TO REGISTER ENABLED to Mode Register for display.
60
Unassigned
ETCCC
61 CACHE
LEVEL
LEAST RECENTLY USED
LEVEL 1/2
62 CACHE
LEVEL
LEAST RECENTLY USED
LEVEL l/3
63 CACHE
LEVEL
LEAST RECENTLY USED
LEVEL 1/4
64 CACHE
LEVEL
LEAST RECENTLY USED
LEVEL 2/3
65 CACHE
LEVEL
LEAST RECENTLY USED
LEVEL'2/4
66 CACHE
LEVEL
LEAST RECENTLY USED
LEVEL 3/4
'67-69
Unassigned
ETCCG
70-71
LOCK UP FAULT TIMER REGISTER
00 = 2 MIL. S.
01 = 4
"
10 = 8
"
11 = 16
"
(32 = MASTER MODE)
Mode Register Decode (Bits 36—71)
Figure 5—9
Sheet 2 of 2
99
REV.
l
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