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7 INTERRUPT AND STANDBY STATUS
7 INTERRUPT AND STANDBY STATUS
Types of interrupts
4 systems and 34 types of interrupts have been
provided for the S1C88655.
External interrupt
•P20–P27 input interrupt (8 types)
Internal interrupt
•Clock timer interrupt (4 types)
•Programmable timer interrupt (16 types)
•Serial interface interrupt (6 types)
Each interrupt source provides an interrupt
factor flag that indicates occurrence of an
interrupt factor and an interrupt enable register
that enables/disables interrupt requests for
controlling interrupt generation. In addition, an
interrupt priority register has been provided for
each interrupt system allowing interrupt
handler routines to set the priority of each
interrupt system to 3 levels.
Figure 7.1 shows the configuration of the
interrupt circuit.
Refer to the explanations of the respective
peripheral circuits for details on each interrupt.
HALT mode
When the program executes the HALT instruc-
tion, the S1C88655 enters HALT mode.
Since the CPU stops operating in HALT mode,
power consumption can be reduced with only
peripheral circuit operation.
The HALT mode is cancelled by initial reset or
an interrupt request, and the CPU restarts
program execution from an exception handler
routine.
See the "S1C88 Core CPU Manual" for the
HALT mode and reactivation sequence.
SLEEP mode
When the program executes the SLP instruction,
the S1C88655 enters SLEEP mode.
Since the CPU and peripheral circuits stop
operating completely in SLEEP mode, power
consumption can be reduced even more than in
HALT mode.
The SLEEP mode is cancelled by initial reset or
an input interrupt from the port. The CPU
reactivates after waiting 128/f
seconds of oscillation stabilization time (the
oscillation stabilization time varies depending
on the operating clock being used when the SLP
instruction is executed). At this time, the CPU
restarts program execution from an exception
handler routine (input interrupt routine).
Note: The oscillation becomes unstable for a while
after SLEEP status is cancelled, the wait
time for restarting the CPU may be longer
than 128/f
or 512/f
OSC1
44
or 512/f
OSC1
OSC3
seconds.
OSC3
EPSON
7.1 Interrupt Generation Conditions
The interrupt factor flags that indicate occurrence
of their respective interrupt factors are provided for
the previously indicated 4 systems and 34 types of
interrupts. They will be set to "1" when the corre-
sponding interrupt factor occurs.
In addition, interrupt enable registers with a 1 to 1
correspondence to each of the interrupt factor flags
are provided. An interrupt is enabled when "1" is
written and interrupt is disabled when "0" is
written.
The CPU manages the enable/disable of interrupt
requests at the interrupt priority level. An interrupt
priority register that sets the priority level is
provided for each of the interrupts of the 4 systems
and the CPU accepts only interrupts above the level
that has been indicated with the interrupt flags (I0
and I1).
Consequently, the following three conditions are
necessary for the CPU to accept the interrupt.
(1) The interrupt factor flag has been set to "1" by
generation of an interrupt factor.
(2) The interrupt enable register corresponding to
the above has been set to "1".
(3) The interrupt priority register corresponding to
the above has been set to a priority level higher
than the interrupt flag (I0 and I1) setting.
The CPU initially samples the interrupt for the first
op-code fetch cycle of each instruction. Thereupon,
the CPU shifts to the exception processing when the
above mentioned conditions have been established.
See the "S1C88 Core CPU Manual" for the exception
processing sequence.
S1C88655 TECHNICAL MANUAL
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