Epson 6200A Core Cpu Manual
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Epson 6200A Core Cpu Manual

Epson 6200A Core Cpu Manual

Core cpu cmos 4-bit single chip microcomputer
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MF297-07a
CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER
S1C6200/6200A
Core CPU Manual

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  • Page 1 MF297-07a CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C6200/6200A Core CPU Manual...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
  • Page 3 Configuration of product number Devices 60N01 Development tools S5U1 60R08 0A01 Packing specifications 00 : Besides tape & reel 0A : TCP BL 0B : Tape & reel BACK 0C : TCP BR 0D : TCP BT 0E : TCP BD 0F : Tape &...

  • Page 5: Table Of Contents

    S1C6200/6200A Core CPU Manual ____________________________________________________ 1 ESCRIPTION 1.1 System Features ... 1 1.2 Instruction Set Features ... 1 1.3 Differences between S1C6200 and S1C6200A ... 1 EMORY AND PERATIONS 2.1 Program Memory (ROM) ... 3 2.1.1 Program counter block ... 4 2.1.2 Flags ...

  • Page 7: S1C6200/6200A Core Cpu Manual

    ESCRIPTION The S1C6200/6200A is the Core CPU of the S1C62 Family of CMOS 4-bit single-chip microcomput- ers. The CPU features a highly-integrated architecture. Memory-mapped peripheral circuits can include RAM, ROM, I/O ports, interrupt controllers, timers and LCD drivers, depending upon the application.
  • Page 8 XHL (8) Stack Pointer (8) 12-bit data bus Fig. 1.1 Block diagram EPSON XP (4) YP (4) Oscillator Interrupt Timing Controller Generator A (4) B (4) TEMPB (5) TEMPA (5) I D Z C S1C6200 CORE CPU S1C6200/6200A CORE CPU MANUAL...

  • Page 9: Memory And Operations

    EMORY AND A single-chip microcomputer using the S1C6200/6200A Core CPU has four major blocks: the program memory (ROM), the data memory (RAM and I/O), the arithmetic logic unit (ALU) and the timing generator circuit. This section describes each of these blocks in detail.

  • Page 10: Program Counter Block

    (8,192 12-bit words max.) Address decoder Program counter block Fig. 2.1.1.1 Program counter configuration Table 2.1.2.1 Flags Flag Menus 1: Enabled 0: Disabled 1: Decimal 0: Hexadecimal 1: Set 0: Ignored 1: Set 0: Ignored EPSON Size Size S1C6200/6200A CORE CPU MANUAL...

  • Page 11: Jump Instructions

    As only the page data specified by NPP is loaded to PCP when a call instruction is executed, subroutine calls between banks are not possible. Jumps between banks can only be made using JP instructions. S1C6200/6200A CORE CPU MANUAL Table 2.1.3.1 Jump instructions...

  • Page 12: Pset Instruction

    The data set by PSET is canceled, and the program jumps to bank 0, page 1, step 9. Bank 0 Page 0 EEE... Bank 0 Page 2 PSET Not effect on destination CALZ of CALZ Fig. 2.1.7.1 The use of the CALZ instruction EPSON S1C6200/6200A CORE CPU MANUAL...

  • Page 13: Ret And Rets Instructions

    Nesting allows efficient usage of the stack area. As the stack area resides in the data memory, care should be taken to ensure that the stack area is not corrupted by other data. S1C6200/6200A CORE CPU MANUAL CALL with PSET Bank 0...

  • Page 14: Data Memory

    Fig. 2.2.1 Data memory configuration Register/Pointer Mnemonic Index Register X Index Register Y Stack Pointer Register Fig. 2.2.1.1 The configuration of the index register IX EPSON XHL or YHL (within page) Memory or I/O Register area Size (bits) S1C6200/6200A CORE CPU MANUAL...
  • Page 15 A,Mn B,Mn Mn,A M(n) Mn,B M(n) M(n) M(n) n: 0 to F S1C6200/6200A CORE CPU MANUAL Fig. 2.2.1.2 The configuration of the index register IY Operation Push-down (SP is decremented) Pop-up (SP is incremented) M(n) M(n) where M(n) is the contents of a data memory location within the register area.

  • Page 16: Alu (Arithmetic Logic Unit) And Registers

    D = 1 : Result of Actual D = 0 : Result of decimal operation result hexadecimal operation ALU output EPSON X: Don't care. Subtraction D = 1 : Result of decimal operation ALU output ALU output S1C6200/6200A CORE CPU MANUAL...

  • Page 17: A And B Registers

    The data in A can be paired with that in B for use as an indirect jump address by the JPBA instruction. 2.4 Timing Generator S1C6200/6200A instructions can be divided into three different types depending on the number of clock cycles per instruction: 5, 7 or 12 clock cycles. The more complex the instruction, the more cycles it requires.

  • Page 18: Interrupts

    2 MEMORY AND OPERATIONS 2.5 Interrupts The S1C6200/6200A can have up to 15 interrupt vectors. When used with peripheral circuits, these allow internal and external interrupts to be processed easily. See Figure 2.5.3.1 through 2.5.3.4. 2.5.1 Interrupt vectors The interrupt vectors are assigned to steps 1 to 15 in page 1 of each bank of the program memory. When an interrupt occurs, the program jumps to the appropriate interrupt vector in the current bank.
  • Page 19 Instruction 5-clock Instrruction Status: Fetch S1C6200/6200A System clock CPU clock Status Instruction 5-clock Instrruction Status: Fetch S1C6200/6200A CORE CPU MANUAL 12-clock Instrruction Interrupt Interrupt processing: 12-clock instruction 7-clock instruction 5-clock instruction 12-clock Instrruction Interrupt Interrupt processing: 12-clock instruction 7-clock instruction...
  • Page 20 INT1 and INT2 are dummy instructions Branches to the top of the interrupt service routine (*2) Fig. 2.5.3.4 Interrupt timing with PSET EPSON INT1 (*1) INT2 (*1) JP (*2) INT2 (*1) JP (*2) INT2 (*1) JP (*2) S1C6200/6200A CORE CPU MANUAL...

  • Page 21: Initial Reset

    When using the model loaded with the S1C6200 Core CPU, set or reset the D flag in the user's initial routine before using an arithmetic instruction. (refer to the SDF and RDF instructions.) S1C6200/6200A CORE CPU MANUAL Table 2.5.4.1 Reset value Bit length Table 2.5.4.2 D (decimal) flag initial setting...

  • Page 22: Instruction Set

    3 INSTRUCTION SET NSTRUCTION This chapter describes the entire instruction set of the S1C6200/6200A Core CPU. A subset is allocated to each device within the S1C62 Family according to the configuration of the device. Therefore not all instructions are available in every device. The relevant information is in the technical manual for each device.

  • Page 23: By Function

    XP r, XH r, XL r, YP r, YH r, YL XH, i XL, i YH, i YL, i S1C6200/6200A CORE CPU MANUAL Operation Code Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation p4, NPP p3~p0...
  • Page 24 0 (Disables Interrupt) SP+1 SP-1 SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) M(SP), SP SP+1 M(SP), SP SP+1 M(SP), SP SP+1 M(SP), SP SP+1 M(SP), SP SP+1 S1C6200/6200A CORE CPU MANUAL...
  • Page 25 ACPX MX, r ACPY MY, r SCPX MX, r SCPY MY, r S1C6200/6200A CORE CPU MANUAL Operation Code Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation M(SP), SP SP+1 M(SP), SP...

  • Page 26: In Alphabetical Order

    NPP, PCS s7~s0 if C=1 NBP, PCP NPP, PCS s7~s0 if C=0 NBP, PCP NPP, PCS s7~s0 if Z=0 NBP, PCP NPP, PCS s7~s0 NBP, PCP NPP, PCS s7~s0 if Z=1 e3~e0, M(X+1) e7~e4, X S1C6200/6200A CORE CPU MANUAL PCSL+1 PCSL+1...
  • Page 27 Y, e LDPX MX, i r, q LDPY MY, i r, q NOP5 NOP7 r, i r, q S1C6200/6200A CORE CPU MANUAL Flag Clock I D Z C M(n3~n0) M(n3~n0) i3~i0 M(X) q, X M(Y) q, Y No operation (5 clock cycles)
  • Page 28 X M(SP), PCSH M(SP+1), PCP M(SP+2) SP+3, PC PC+1 d2, d2 d1, d1 d0, d0 C, C C, d2 d3, d1 d2, d0 d1, C F i3~i0 M(X)-r-C, X M(Y)-r-C, Y 1 (Decimal Adjuster ON) FVi3~i0 S1C6200/6200A CORE CPU MANUAL...

  • Page 29: By Operation Code

    D0F to D3F D40 to D7F r, i D80 to DBF r, i DC0 to DFF r, i E00 to E3F r, i S1C6200/6200A CORE CPU MANUAL Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation NBP, PCP NPP, PCS...
  • Page 30 Y M(X) M(X)+r+C, X M(Y) M(Y)+r+C, Y M(X) M(X)-r-C, X M(Y) M(Y)-r-C, Y FVi3~i0 1 (Decimal Adjuster ON) 1 (Enables Interrupt) F i3~i0 0 (Disables Interrupt) 0 (Decimal Adjuster OFF) M(n3~n0) M(n3~n0)+1 M(n3~n0) M(n3~n0)-1 M(n3~n0) S1C6200/6200A CORE CPU MANUAL...
  • Page 31 SPH, r FE4 to FE7 r, SPH JPBA FF0 to FF3 SPL, r FF4 to FF7 r, SPL HALT NOP5 NOP7 S1C6200/6200A CORE CPU MANUAL Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation M(n3~n0) M(n3~n0) M(n3~n0) SP-1, M(SP)

  • Page 32: Operands

    POP F instruction. When an interrupt is generated, the I flag is automatically reset. It is not automatically set at the end of the interrupt service routine. Table 3.2.1 Values of r and q r1 or q1 r0 or q0 EPSON S1C6200/6200A CORE CPU MANUAL...

  • Page 33: Instruction Types

    Instructions are divided into six types according to the size of the operand. Op-code (II) Op-code (III) Op-code (IV) Op-code Op-code (VI) 3.5 Instruction Descriptions This section describes S1C6200/6200A instructions in alphabetical order. S1C6200/6200A CORE CPU MANUAL 8-bit operand 6-bit operand 5-bit operand 4-bit operand 2-bit operand Op-code EPSON 3 INSTRUCTION SET...

  • Page 34: Acpx Mx,R Add With Carry R-Register To M(X), Increment X By

    0010 0001 0000 1110 0000 1111 1000 1011 0100 0100 0110 0110 0010 0010 EPSON F28H to F2BH 1010 0010 0100 0110 1111 0111 0100 1000 F2CH to F2FH 0010 0001 0001 0000 1011 1010 0110 0010 S1C6200/6200A CORE CPU MANUAL...
  • Page 35 Adds the carry bit and the contents of the q-register to the r-register. Example: A register B register Memory (MX) Memory (MY) C flag Z flag S1C6200/6200A CORE CPU MANUAL to i ADC MX,3 0100 1000 1001 1001 ADC MY,A...
  • Page 36 Adds the carry bit and immediate data i to XL, the four low-order bits of XHL. Example: XL register C flag Z flag to i ADC XH,2 ADC XH,4 1001 1100 to i ADC XL,3 ADC XL,0EH 0000 0100 EPSON A00H to A0FH 0000 A10H to A1FH 0010 S1C6200/6200A CORE CPU MANUAL...
  • Page 37 Not affected Description: Adds the carry bit and immediate data i to YL, the four low-order bits of YHL. Example: YL register C flag Z flag S1C6200/6200A CORE CPU MANUAL to i ADC YH,3 ADC YH,6 1010 1110 to i...
  • Page 38 Z flag to i ADD A,5 1010 1111 0110 0110 ADD A,MY 0010 1111 0100 0100 0111 0111 1101 1101 EPSON C00H to C3FH ADD MY,2 1111 1000 A80H to A8FH ADD MX,B 1111 0100 1011 1101 S1C6200/6200A CORE CPU MANUAL...

  • Page 39: And R,I

    Performs a logical AND operation between the contents of the q-register and the contents of the r-register. The result is stored in the r-register. Example: A register B register Memory (MX) Memory (MY) C flag Z flag S1C6200/6200A CORE CPU MANUAL to i AND A,5 0110 0100 1000 1000 AND MX,A 0100...
  • Page 40 1010 xxxx 0010 xxxx 1111 EPSON PCSL + 1, SP SP - 3, 400H to 4FFH CALL 10H 0110 0001 0000 0110 0011 0010 1101 PCSL + 1, SP SP - 3, 500H to 5FFH S1C6200/6200A CORE CPU MANUAL...

  • Page 41: Cp R,I

    3. When Z = 0 and C = 1 then q > r Example: A register B register Memory (MY) C flag Z flag S1C6200/6200A CORE CPU MANUAL to i ; otherwise, reset. to i ; otherwise, reset. CP A,4 CP MX,7...

  • Page 42: Cp Xh,I

    CP XH,2 CP XH,4 0100 0100 to i ; otherwise, reset. to i ; otherwise, reset. CP XL,7 CP XL,9 1001 1001 EPSON A40H to A4FH CP XH,9 0100 0100 A50H to A5FH CP XL,0AH 1001 1001 S1C6200/6200A CORE CPU MANUAL...

  • Page 43: Cp Yh,I

    2. When Z = 1 and C = 0 then i = YL Example: 3. When Z = 0 and C = 1 then i > YL Example: YL register C flag Z flag S1C6200/6200A CORE CPU MANUAL to i to i ; otherwise, reset. to i ; otherwise, reset. CP YH,0AH...
  • Page 44 Z flag to n ) - 1 DEC M0 DEC M2 1001 1000 0000 0000 0001 0001 DEC SP 1011 0001 1011 0000 EPSON F70H to F7FH DEC M0FH 1000 1000 1111 1111 0001 0000 FCBH S1C6200/6200A CORE CPU MANUAL...

  • Page 45: Disable Interrupts

    Clock Cycles: Flag: C – Not affected Z – Not affected D – Not affected I – Description: Enables all interrupts. Example: C flag Z flag D flag I flag S1C6200/6200A CORE CPU MANUAL F57H F48H EPSON 3 INSTRUCTION SET...
  • Page 46 FAN A,B FAN MX,B 1000 1000 1010 1010 0101 0101 1110 1110 EPSON D80H to DBFH FAN B,2 1000 1000 0100 0100 1000 1000 F10H to F1FH FAN A,MY 1000 1000 1010 1010 0101 0101 1110 1110 S1C6200/6200A CORE CPU MANUAL...
  • Page 47 Not affected Description: The contents of the data memory location addressed by Mn is incremented by 1. Example: Memory (01H) Memory (03H) Memory (0DH) C flag Z flag S1C6200/6200A CORE CPU MANUAL Instruction State HALT 0001 HALT 0001 0001 to n...

  • Page 48: Inc Sp

    Increments the contents of register X by 1. This operation does not affect the flags. Example: X register C flag Z flag FDBH INC SP 1110 1111 1111 0000 EE0H INC X 1111 1110 1111 1111 EPSON S1C6200/6200A CORE CPU MANUAL...

  • Page 49: Inc Y

    The b-register contains the four high-order bits of the address and the a- register contains the four low-order bits of the address. Example: A register B register S1C6200/6200A CORE CPU MANUAL INC Y 1011 0111 1011 1000 NBP, PCP...
  • Page 50 1000 1111 1001 0000 EPSON if C = 1 200H to 2FFH JP C,10H 0010 0110 0110 0110 0011 1110 0001 0000 0000 0000 if C = 0 300H to 3FFH JP NC,10H 0001 0001 0001 0000 S1C6200/6200A CORE CPU MANUAL...
  • Page 51 Z – Not affected D – Not affected I – Not affected Description: Unconditional jump to the destination address specified by the 8-bit operand. Example: S1C6200/6200A CORE CPU MANUAL NBP, PCP NPP, PCS to s JP NZ,10H 0000 0000 0000 0000...

  • Page 52: Lbpx Mx,E Load Immediate Data E To Memory, And Increment X By

    0111 0111 EPSON if Z = 1 600H to 6FFH JP Z,10H 0101 1011 1011 1011 0000 0100 0001 0000 0000 0000 0110 0110 X + 2 900H to 9FFH 0010 0010 1000 0001 0110 0011 S1C6200/6200A CORE CPU MANUAL...

  • Page 53: Ld A,Mn

    I – Not affected Description: Loads the contents of the data memory location addressed by Mn into the B- register. Example: B register Memory (07H) Memory (08H) S1C6200/6200A CORE CPU MANUAL to n LD A,M5 0100 1111 1111 1111 0100 0100...
  • Page 54 Memory (00H) Memory (01H) LD M0AH,A LD M0BH,A 0110 0110 0100 0110 1011 1011 LD M0,B 0100 0100 1011 0100 1111 1111 EPSON F80H to F8FH 0110 0110 0110 F90H to F9FH LD M1,B 0100 0100 0100 S1C6200/6200A CORE CPU MANUAL...
  • Page 55 Loads the contents of the q-register into the r-register. X is incremented by 1. Incrementing X does not affect the flags. Example: X register A register B register Memory (MY) S1C6200/6200A CORE CPU MANUAL to i X + 1 LDPX MX,7 LDPX MX,0AH 1000 0011 1000 0100...
  • Page 56 0111 0010 0010 Y + 1 LDPY A,B LDPY MX,B 0100 1000 0100 1001 1010 1000 1000 1000 0010 0010 EPSON E70H to E7FH 0010 1111 0111 0000 EF0H to EFFH 0100 1010 1000 1000 1000 S1C6200/6200A CORE CPU MANUAL...
  • Page 57 D – Not affected I – Not affected Description: The contents of the q-register are loaded into the r-register. Example: A register B register Memory (MY) S1C6200/6200A CORE CPU MANUAL LD A,6 0101 0110 1001 1001 LD A,B 0010 0000 0000...
  • Page 58 A register Memory (MY) FE4H to FE7H LD MX,SPH LD A,SPH 0111 0111 0111 0000 0000 0111 1100 0111 0111 FF4H to FF7H LD A,SPL LD MY,SPL 1001 1001 1001 0010 1001 1001 0000 0000 1001 EPSON S1C6200/6200A CORE CPU MANUAL...
  • Page 59 Not affected I – Not affected Description: Loads the four low-order bits of register X into the r-register. Example: XL register A register Memory (MY) S1C6200/6200A CORE CPU MANUAL EA4H to EA7H LD B,XH LD MX,XH 1010 1010 1010 0010 1010...
  • Page 60 A register Memory (MY) EA0H to EA3H LD MX,XP LD A,XP 1111 1111 1111 0010 0010 1111 0101 1111 1111 EB4H to EB7H LD A,YH LD MY,YH 1010 1010 1010 1100 1010 1010 1110 1110 1010 EPSON S1C6200/6200A CORE CPU MANUAL...
  • Page 61 I – Not affected Description: Loads the 4-bit page part of index register IY into the r-register. Example: YP register B register Memory (MY) S1C6200/6200A CORE CPU MANUAL EB8H to EBBH LD B,YL LD MX,YL 0000 0000 0000 0110 0000...
  • Page 62 B register Memory (MX) LD SPH,A 1001 0011 0011 0011 1100 1100 LD SPL,B 1011 0111 0111 0111 1111 1111 EPSON FE0H to FE3H LD SPH,MY 1100 0011 1100 FF0H to FF3H LD SPL,MX 1111 0111 1111 S1C6200/6200A CORE CPU MANUAL...
  • Page 63 I – Not affected Description: Loads the contents of the r-register into the four high-order bits of register X. Example: XH register A register Memory (MY) S1C6200/6200A CORE CPU MANUAL to e , XL to e LD X,6FH 0000 0110 1011...
  • Page 64 B register Memory (MX) E88H to E8BH LD XL,MY LD XL,A 0000 0010 1011 1011 1011 1011 0010 0010 0010 E80H to E83H LD XP,B LD XP,MX 1001 0001 1011 0001 0001 0001 1011 1011 1011 EPSON S1C6200/6200A CORE CPU MANUAL...
  • Page 65 I – Not affected Description: Loads the contents of the r-register into the four high-order bits of register Y. Example: YH register B register Memory (MX) S1C6200/6200A CORE CPU MANUAL to e , YL to e LD Y,E1H 0001 1110 1100...
  • Page 66 A register Memory (MX) E98H to E9BH LD YL,B LD YL,MX 1011 1010 0111 1010 1010 1010 0111 0111 0111 E90H to E93H LD YP,MX LD YP,A 0011 0000 0100 0100 0100 0100 0000 0000 0000 EPSON S1C6200/6200A CORE CPU MANUAL...

  • Page 67: No Operation For 5 Clock Cycles

    D – Not affected I – Not affected Description: Increments the program counter by 1. Has no other effect for 7 clock cycles. Example: S1C6200/6200A CORE CPU MANUAL 1 0 1 1 FFBH NOP5 0011 0011 0001 0011 0001 0100...
  • Page 68 Memory (MX) Z flag 1 1 1 1 NOT A 1001 0110 1111 1111 to i OR B,5 0100 0101 0011 0011 EPSON D0FH to D3FH NOT MY 0110 0000 CC0H to CFFH OR MX,0BH 0101 0111 S1C6200/6200A CORE CPU MANUAL...

  • Page 69: Or R,Q

    Description: Replaces the flags (F) with the contents of the data memory location addressed by the stack pointer. SP is incremented by 1. Example: Memory (C0H) Flags (I,D,Z,C) S1C6200/6200A CORE CPU MANUAL OR MY,0 0011 0011 0000 0000 SP + 1...
  • Page 70 SP + 1 0 0 r FD0H to FD3H M(SP) = POP B 1001 1001 0101 1001 SP + 1 0 1 0 1 FD5H M(SP) = POP XH 0110 0110 0010 0110 EPSON = r-register = XH S1C6200/6200A CORE CPU MANUAL...

  • Page 71: Pop Xl

    Loads the contents of the data memory location addressed by the stack pointer into XP, the 4-bit page part of IX. SP is incremented by 1. Example: Memory (B4H) XP register S1C6200/6200A CORE CPU MANUAL SP + 1 0 1 1 0 FD6H M(SP) =...

  • Page 72: Pop Yh

    SP + 1 1 0 0 0 FD8H M(SP) = POP YH 1101 1101 0010 1101 SP + 1 1 0 0 1 FD9H POP YL M(SP) = 0100 0100 0101 0100 EPSON = YH = YL S1C6200/6200A CORE CPU MANUAL...
  • Page 73 Loads the most-significant bit of the 5-bit immediate data p to the new bank pointer (NBP) and the four low-order bits to the new page pointer (NPP). Example: S1C6200/6200A CORE CPU MANUAL SP + 1 0 1 1 1 POP YP...
  • Page 74 A register 1 0 1 0 FCAH M(SP) = PUSH F 0100 0001 0001 0001 0 0 r FC0H to FC3H PUSH A M(SP) = 1000 0010 0010 0010 EPSON flag flag flag flag = r-register S1C6200/6200A CORE CPU MANUAL...

  • Page 75: Push Xh

    Decrements the stack pointer by 1 and loads the contents of XL, the four low-order bits of XHL, into the data memory location addressed by SP. Example: Memory (CFH) XL register S1C6200/6200A CORE CPU MANUAL 0 1 0 1 FC5H M(SP) = PUSH XH...

  • Page 76: Push Xp

    Example: Memory (BEH) YH register 0 1 0 0 FC4H M(SP) = PUSH XP 0011 0000 0000 0000 1 0 0 0 FC8H M(SP) = PUSH YH 0100 0001 0001 0001 EPSON = XP = YH S1C6200/6200A CORE CPU MANUAL...

  • Page 77: Push Yl

    Decrements the stack pointer by 1 and loads the contents of YP, the page part of IY, into the data memory location addressed by SP. Example: Memory (BFH) YP register S1C6200/6200A CORE CPU MANUAL 1 0 0 1 FC9H M(SP) = PUSH YL...

  • Page 78: Reset Carry Flag

    Example: A register D flag C flag Z flag 1 1 1 0 F5EH ADD A,4 1101 0001 0001 1 0 1 1 F5BH ADD A,8 LD A,6 0110 0100 0100 EPSON ADD A,8 0110 1110 S1C6200/6200A CORE CPU MANUAL...

  • Page 79: Return From Subroutine

    RET command. X is incremented by 2. Example: Example: Memory (SP) Memory (SP+1) Memory (SP+2) X register Memory (2AH) Memory (2BH) S1C6200/6200A CORE CPU MANUAL M(SP), PCSH M(SP+1), PCP 1 1 1 1 1101 0010 1000 1101 0010 1101 1101...
  • Page 80 1 1 1 0 RETS 0110 0000 1001 0000 0000 0111 0110 0110 0000 0000 0000 0000 C, C r-register RLC A 0011 0111 EPSON M(SP+2), SP SP + 3, PC FDEH AF0H to AFFH r-register S1C6200/6200A CORE CPU MANUAL PC + 1...
  • Page 81 Reset if i Description: Performs a logical AND operation between immediate data i and the contents of the flags. The result is stored in each respective flag. Example: Flags (I,D,Z,C) S1C6200/6200A CORE CPU MANUAL 1 1 r r-register RRC MY 1010 1101 to i is zero;...
  • Page 82 Subtracts the carry flag and immediate data i from the r-register. Example: A register Memory (MY) C flag Z flag 1 1 0 1 ADD A,3 1101 0000 to i SBC A,9 SBC MY,0DH 1000 1111 1110 1110 EPSON F5DH 0000 D40H to D7FH 1111 0000 S1C6200/6200A CORE CPU MANUAL...

  • Page 83: Sbc R,Q

    C – Z – Not affected D – Not affected I – Not affected Description: Sets the C (carry) flag. Example: C flag S1C6200/6200A CORE CPU MANUAL AB0H to ABFH SBC A,B SBC MY,MX 1110 1011 1011 0010 0010 0010 1001...
  • Page 84 0101 0000 0101 0001 0110 0100 0010 0010 M(Y) - r - C, Y Y + 1 1 1 r SCPY MY,A 1111 1111 0000 0000 0111 0100 0010 0010 EPSON F38H to F3BH F3CH to F3FH S1C6200/6200A CORE CPU MANUAL...

  • Page 85: Set Decimal Flag

    Performs a logical OR operation between immediate data i and the contents of the flags. The results are stored in each respective flag. Example: Flags (C,Z,D,I) S1C6200/6200A CORE CPU MANUAL 0 1 0 0 to i is 1; otherwise, not affected.
  • Page 86 B register C flag Z flag 1 0 0 1 FF9H Instruction State 0100 0011 0000 0100 0011 0001 SLEEP NOP5 0001 0000 0001 AA0H to AAFH SUB A,B 1100 1001 0011 0011 EPSON I flag S1C6200/6200A CORE CPU MANUAL...

  • Page 87: Set Zero Flag

    Performs an exclusive-OR operation between immediate data i and the contents of the r-register. The result is stored in the r-register. Example: A register Memory (MX) Z flag S1C6200/6200A CORE CPU MANUAL 0 0 1 0 to i XOR A,12 0110 1010...
  • Page 88 Operation: OP-Code: Type: Clock Cycles: Flag: C – Z – D – I – Description: Example: XOR A,MY 0100 1100 1111 1111 0111 0111 1000 1000 EPSON AE0H to AEFH XOR MX,B 1100 1111 1000 1000 S1C6200/6200A CORE CPU MANUAL...
  • Page 89 Logical AND Clock Cycles: ... Logical OR Flag: C – ... Exclusive-OR Z – ... Reset flag D – ... Set flag I – ... Set/reset flag Description: ... Decimal addition/subtraction Example: S1C6200/6200A CORE CPU MANUAL EPSON 3 INSTRUCTION SET...

  • Page 90: Appendix

    12.5 to 24.5 13 to 25 12.5 to 19.5 13 to 20 12.5 to 17.5 13 to 18 14 to 15 14 to 15 12.5 to 24.5 13 to 25 12.5 to 22.5 13 to 23 S1C6200/6200A CORE CPU MANUAL...
  • Page 91 Fetch Clock Status Instruction PSET Interrupt processing: Status: Fetch Fig. A2.2.1 Timing chart of S1C6200A interrupt S1C6200/6200A CORE CPU MANUAL APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU 12-clock Instrruction Interrupt Interrupt processing: 12-clock instruction 7-clock instruction 5-clock instruction Execute Note:...

  • Page 92: Instruction

    Particularly when there are multiple interrupt factor flags in the same address, extra caution is required. S1C6200A Possible Fetch Execute Execute next instruction CPU Core S1C6200A Possible EPSON S1C6200 Not possible Fetch Execute Fetch "1" is written to the interrupt mask register INT1(interrupt processing) S1C6200 Not possible S1C6200/6200A CORE CPU MANUAL...

  • Page 93: B. I Nstruction I Ndex

    JP NC,s JP NZ,s JP s JP Z,s S1C6200/6200A CORE CPU MANUAL NDEX Add with carry r-register to M(Y), increment Y by 1 ... 28 Add with carry immediate data i to r-register ... 29 Add with carry q-register to r-register ... 29 Add with carry immediate data i to XH ...
  • Page 94 Pop stack data into XP ... 65 Pop stack data into YH ... 66 Pop stack data into YL ... 66 Pop stack data into YP ... 67 Page set ... 67 Push flag onto stack ... 68 EPSON S1C6200/6200A CORE CPU MANUAL...
  • Page 95 SCPY MY,r SET F,i SUB r,q XOR r,i XOR r,q S1C6200/6200A CORE CPU MANUAL Push r-register onto stack ... 68 Push XH onto stack ... 69 Push XL onto stack ... 69 Push XP onto stack ... 70 Push YH onto stack ... 70 Push YL onto stack ...
  • Page 96 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 10F, No. 287, Nanking East Road, Sec. 3 Taipei Phone: 02-2717-7360 Fax: 02-2712-9164 Telex: 24444 EPSONTB HSINCHU OFFICE 13F-3, No.
  • Page 97 S1C6200/6200A Core CPU Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com First issue February, 1989 Printed February, 2001 in Japan...

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