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• Capture operation (free running mode)
The following figure illustrates the operation of the capture register when the capture trigger is input.
Figure 7-15. CRn1 Capture Operation with Rising Edge Specified
Count clock
TMn
TIn0
Rising edge detection
CRn1
INTTMn1
Remark n = 0, 1
Figure 7-16. Timing of Pulse Width Measurement with Free Running Counter (with both edges specified)
t
Count clock
TMn count value
0000H
0001H
TIn0 pin input
Value loaded to
CRn1
INTTMn1
TIn1 pin input
Value loaded to
CRn0
INTTMn0
OVFn
Remark n = 0, 1
164
CHAPTER 7
TIMER/COUNTER FUNCTION
n − 3
n − 2
n − 1
D0
D0+1
D1
D1+1
D0
D1
D1
(D1 − D0) × t
n
n + 1
n
FFFFH
0000H
D2
(10000H − D1 + D2) × t
(10000H − D1 + (D2 + 1) × t
D2+1
D2+2
D3
D2
D2+1
(D3 − D2) × t
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