Sign In
Upload
Manuals
Brands
NEC Manuals
Microcontrollers
V850/SA1 mPD70F3017
NEC V850/SA1 mPD70F3017 Manuals
Manuals and User Guides for NEC V850/SA1 mPD70F3017. We have
1
NEC V850/SA1 mPD70F3017 manual available for free PDF download: Preliminary User's Manual
NEC V850/SA1 mPD70F3017 Preliminary User's Manual (387 pages)
32-/16-Bit Single-Chip Microcontrollers
Brand:
NEC
| Category:
Microcontrollers
| Size: 1.74 MB
Table of Contents
Table of Contents
9
Chapter 1 Introduction
21
General
21
Features
21
Application Fields
23
Ordering Information
23
Pin Configuration (Top View)
24
Function Blocks
27
Internal Block Diagram
27
On-Chip Units
28
Chapter 2 Pin Functions
31
List of Pin Functions
31
Pin States
37
Description of Pin Functions
38
Pins' I/O Circuit Types and Handling When Not Used
49
Pins' I/O Circuits
51
Chapter 3 Cpu Functions
53
Features
53
CPU Register Set
54
Program Register Set
55
System Register Set
56
Operation Modes
58
Address Space
59
CPU Address Space
59
Image (Virtual Address Space)
60
Wrap-Around of CPU Address Space
61
Memory Map
62
Area
63
Interrupt/Exception Table
64
External Memory Area (When Expanded to 64 K, 256 K, or 1 Mbytes)
67
External Memory Area (When Expanded to 4 Mbytes)
68
External Expansion Mode
69
Memory Expansion Mode Register (MM) Format
70
Memory Address Output Mode Register (MAM) Format
71
Recommended Use of Address Space
72
Recommended Memory Map (Flash Memory Internal Version)
74
Peripheral I/O Registers
75
Specific Registers
80
Chapter 4 Bus Control Function
83
Features
83
Bus Control Pins and Control Register
83
Bus Control Pins
83
Control Register
84
Bus Access
84
Number of Access Clocks
84
Bus Width
85
Memory Block Function
86
Wait Function
87
Programmable Wait Function
87
External Wait Function
88
Relations between Programmable Wait and External Wait
88
Idle State Insertion Function
89
Bus Hold Function
90
Outline of Function
90
Bus Hold Procedure
91
Operation in Power Save Mode
91
Bus Timing
92
Bus Priority
99
Memory Boundary Operation Condition
99
Program Space
99
Data Space
99
Chapter 5 Interrupt/Exception Processing Function
101
Features
101
Interrupt Source List
102
Non-Maskable Interrupt
104
Accepting Operation
105
Accepting Non-Maskable Interrupt Request
106
Restore
107
NP Flag
108
Noise Elimination Circuit of NMI Pin
108
Edge Detection Function of NMI Pin
109
Maskable Interrupts
110
Operation
110
Maskable Interrupt Processing
111
Restore
112
Priorities of Maskable Interrupts
113
Example of Interrupt Nesting Process
114
Example of Processing Interrupt Requests Simultaneously Generated
116
Interrupt Control Register (Xxicn)
117
In-Service Priority Register (ISPR)
119
Maskable Interrupt Status Flag
119
Watchdog Timer Mode Register (WDTM)
120
Noise Elimination
120
Edge Detection Function
121
Software Exception
122
Operation
122
Restore
123
EP Flag
124
Exception Trap
124
Illegal Op Code Definition
124
Operation
124
Restore
125
RETI Instruction Processing
126
Priority Control
127
Priorities of Interrupts and Exceptions
127
Multiple Interrupt Processing
127
Periods Where Interrupt Is Not Acknowledged
130
Interrupt Latency Time
130
Chapter 6 Clock Generation Function
131
General
131
Composition
131
Clock Output Function
132
Control Registers
132
Format of Power Saving Control Register (PSC)
134
Power Saving Functions
135
General
135
HALT Mode
136
Operating Statuses During HALT Mode
137
IDLE Mode
139
Software STOP Mode
141
Oscillation Stabilization Time
142
Chapter 7 Timer/Counter Function
145
16-Bit Timer (TM0, TM1)
145
Overview
145
Function
145
Block Diagram of TM0 and TM1
146
Configuration
147
Valid Edge of Tin0 Pin and Capture Trigger of Crn0
148
Timer 0, 1 Control Register
150
Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1)
151
Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1)
153
Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1)
155
Format of Prescaler Mode Register 0 (PRM0)
156
Format of Prescaler Mode Register 1 (PRM1)
157
Operation
158
Operation as Interval Timer (16 Bits)
158
Configuration of Interval Timer
159
PPG Output Operation
160
Pulse Width Measurement
161
Configuration for Pulse Width Measurement with Free Running Counter
162
Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter
163
Crn1 Capture Operation with Rising Edge Specified
164
Control Register Settings for Pulse Width Measurement by Restarting
167
Operation as External Event Counter
168
Operation to Output Square Wave
169
Control Register Settings in Square Wave Output Mode
170
Operation to Output One-Shot Pulse
171
Control Register Settings for One-Shot Pulse Output with Software Trigger
172
Timing of One-Shot Pulse Output Operation with Software Trigger
173
Control Register Settings for One-Shot Pulse Output with External Trigger
174
Cautions
175
Timing after Changing Compare Register During Timer Count Operation
176
Operation Timing of Ovfn Flag
177
8-Bit Timer (TM2-TM5)
178
Functions
178
Configuration
179
Timer N Control Register
181
Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5)
182
Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5)
183
Operation
185
Operating as an Interval Timer (8-Bit Operation)
185
Operating as External Event Counter
187
Operating as Square Wave Output (8-Bit Resolution)
188
Operating as 8-Bit PWM Output
189
Timing of PWM Output
190
Timing of Operation Based on Crn0 Transitions
191
Cascade Connection Mode with 16-Bit Resolution
193
Cautions
194
Chapter 8 Watch Timer
195
Function
195
Configuration
196
Watch Timer Control Register
197
Operation
198
Operation as Watch Timer
198
Operation as Interval Timer
199
Chapter 9 Watchdog Timer
201
Functions
201
Runaway Detection Time for Watchdog Timer
202
Configuration
203
Watchdog Timer Control Register
203
Format of Watchdog Timer Clock Selection Register (WDCS)
204
Format of Watchdog Timer Mode Register (WDTM)
205
Operation
206
Operating as Watchdog Timer
206
Operating as Interval Timer
207
Standby Function Control Register
208
Chapter 10 Serial Interface Function
209
Overview
209
3-Wire Serial I/O (CSI0-CSI2)
209
Configuration
210
Csin Control Registers
211
Format of Serial Clock Selection Registers 0-2 (CSIS0-CSIS2)
212
Operations
213
Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2)
214
Timing of 3-Wire Serial I/O Mode
215
I C Bus ( Μ Μ Μ Μ PD703015Y, 70F3017Y)
217
Configuration
220
I C Control Register
222
Format of IIC Control Register (IICC0)
223
Format of IIC Status Register (IICS0)
227
Format of IIC Clock Select Register (IICCL0)
230
I C Bus Mode Functions
232
Pin Configuration Diagram
232
I C Bus Definitions and Control Methods
233
Start Conditions
233
Address
234
Transfer Direction Specification
235
ACK Signal
236
Stop Condition
237
Wait Signal
238
I C Interrupt Requests (INTIIC0)
240
Interrupt Request (INTIIC0) Generation Timing and Wait Control
260
Address Match Detection Method
261
Error Detection
262
Extension Code
262
Arbitration
263
Arbitration Timing Example
264
Wake up Function
265
Communication Reservation
266
Communication Reservation Timing
267
Timing for Accepting Communication Reservations
268
Communication Reservation Flow Chart
269
Other Cautions
270
Communication Operations
271
Slave Operation Flow Chart
272
Timing of Data Communication
273
Asynchronous Serial Interface (UART0, UART1)
280
Configuration
280
Block Diagram of Uartn
281
Uartn Control Registers
282
Format of Asynchronous Serial Interface Mode Register 0, 1 (ASIM0, ASIM1)
283
Format of Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1)
284
Format of Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)
285
Format of Baud Rate Generator Mode Control Registers 0, 1 (BRGMC0, BRGMC1)
286
Operations
287
Asynchronous Serial Interface (Uartn) Mode
288
Relation between Main Clock and Baud Rate
293
Error Tolerance (When K = 0), Including Sampling Errors
294
Format of Transmit/Receive Data in Asynchronous Serial Interface
295
Timing of Asynchronous Serial Interface Transmit Completion Interrupt
297
Timing of Asynchronous Serial Interface Receive Completion Interrupt
298
Receive Error Timing
299
Standby Function
300
Chapter 11 A/D Converter
301
Function
301
Block Diagram of A/D Converter
302
Configuration
303
Control Registers
305
Format of Analog Input Channel Specification Register (ADS)
307
Operation
308
Basic Operation
308
Basic Operation of A/D Converter
309
Input Voltage and Conversion Result
310
A/D Converter Operation Mode
311
A/D Conversion by Hardware Start (with Falling Edge Specified)
312
A/D Conversion by Software Start
313
Notes on Using A/D Converter
314
Processing of Analog Input Pin
315
A/D Conversion End Interrupt Generation Timing
316
Chapter 12 Dma Functions
317
Functions
317
Transfer Completion Interrupt Request
317
Control Registers
317
Format of DMA On-Chip RAM Address Registers 0 to 2 (DRA0 to DRA2)
318
Format of DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2)
319
Chapter 13 Real-Time Output Function (Rto)
321
Function
321
Configuration
322
RTO Control Registers
323
Format of Real-Time Output Port Mode Register (RTPM)
324
Format of Real-Time Output Port Control Register (RTPC)
325
Operation
326
Usage
327
Notes
327
Chapter 14 Port Function
329
Port Configuration
329
Port Pin Function
329
Port 0
329
Format of Port 0 Mode Register (PM0)
331
Format of Rising Edge Enable Register (EGP0)
332
Port 1
333
Format of Port 1 Mode Register (PM1)
334
Format of Pull-Up Resistance Option Register 1 (PU1)
335
Port 2
336
Format of Port 2 Mode Register (PM2)
337
Format of Pull-Up Resistance Option Register 2 (PU2)
338
Port 3
339
Format of Port 3 Mode Register (PM3)
340
Ports 4 and 5
341
Port 6
343
Format of Port 6 Mode Register (PM6)
344
Ports 7 and 8
345
Port 9
346
Format of Port 9 Mode Register (PM9)
347
Port 10
348
Format of Port 10 Mode Register (PM10)
349
Port 11
350
Format of Port 11 (P11)
351
Format of Port 11 Mode Register (PM11)
352
Port 12
353
Format of Port 12 Mode Register (PM12)
354
Format of Port 12 Mode Control Register (PMC12)
355
Chapter 15 Reset Function
357
General
357
Pin Operations
357
CHAPTER 16 FLASH MEMORY ( Μ Μ Μ Μ PD70F3017, 70F3017Y)
359
Features
359
Writing by Flash Writer
359
Programming Environment
360
Communication System
360
Pin Connection
362
VPP Pin
362
Serial Interface Pin
362
RESET Pin
364
Port Pin
364
Other Signal Pins
364
Power Supply
364
Programming Method
365
Flash Memory Control
365
Flash Memory Programming Mode
365
Selection of Communication Mode
366
Communication Command
366
Resources Used
367
Appendix Aregister Index
369
Appendix Blist of Instrution Set
375
Appendix Cindex
383
Advertisement
Advertisement
Related Products
NEC V850/SA1 mPD70F3017Y
NEC mPD70F3089Y
NEC MPD70F3032A
NEC MPD70F3035A
NEC MPD70F3032AY
NEC MPD70F3035AY
NEC MPD70F3033A
NEC MPD70F3037A
NEC MPD70F3033AY
NEC MPD70F3037AY
NEC Categories
Monitor
Projector
Server
Telephone
Computer Hardware
More NEC Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL