A/D Converter - Fujitsu MB89140 Series Hardware Manual

A/D CONVERTER

P17/ADST
P13/ANB
P12/ANA
P11/AN9
P10/AN8
P07/AN7
P06/AN6
Channel
P05/AN5 selector
P04/AN4
P03/AN3
P02/AN2
P01/AN1
P00/AN0
AV
CC
AV
SS
HARDWARE CONFIGURATION

2.12 A/D CONVERTER

16.5 µs conversion time (at 8 MHz and maximum gear speed)
10-bit resolution
RC sequential comparison A/D converter with sample and hold circuit
Analog input can be selected from 12 channels by the program.
End detection by interrupt or software polling
Starting by software, by external pin trigger, or by timer unit can be se-
lected by the program.
Block Diagram
Selector
Comparator
Sample and
hold circuit
D/A
converter
Fig. 2.41 A/D Converter Block Diagram
Register list
A/D converter consists of A/D control status registers 1 and 2 and ADC data
register (ADCD).
Address: 001E
H
Address: 001F
H
Address: 0020
H
Address: 0021
H
2-76
Control Logic
ADDH and ADDL
ADC1 and ADC2
IRQB
8 bit
ADC1
R/W AD control states register 1
ADC2
R/W AD control states register 2
ADDH
R/W AD control data register (H)
ADDL
R/W AD control data register (L)
Internal
data bus