Vme Control; Table 3-13 Register Definitions Offset From Bar0 - GE VMIVME-7807 Series Hardware Reference Manual

3.6 VME Control

Table 3‐13 shows the register definitions for the VMIVME‐7807/VME‐7807RC
(offset from BAR0).

Table 3-13 Register Definitions Offset from BAR0

Register and Offset Bit Name
VMECOMM
MEC_SEL
Offset 0x00
SEC_SEL
ABLE
BTO
BTOV [1:0]
BERRI
BERRST
SFENA
Unused
BPENA
VBENA
Unused
VBAM
VME_ADDR
0x04
Unused
SEC_SEL
VBAR
VME_ADDR
0x08
Please refer to Table 3‐1, "PCI Configuration Space Registers," on page 33 for
more information concerning BAR0.
Bit Definition
0 Master Big-Endian Enable bit
1=Big Endian, 0=Little Endian
1 Slave Big-Endian Enable bit
1=Big Endian, 0=Little Endian
2 Auxiliary BERR Logic Enable bit
1=Aux. BERR Enabled, 0=Aux. BERR Disabled
3 Bus Error Timer Enabled
1=Enable, 0=Disabled
5:4 Timeout Value
00 - 16 μs
01 - 64 μs
10 - 256 μs
11 - 1.00 ms
6 BERR Interrupt Enable
1=Interrupt Enabled, 0=Interrupt Disabled
7 BERR Status Read/Clear bit
1=Clear BERR status, 0=Do nothing
8 Enables generation of VME SYSFAIL upon WDT
timeout
1=Enable SYSFAIL generation, 0=Disable
9 Not Used
10 Endian Conversion Bypass bit
1=bypass, 0=Not bypassed
11 VME Enable bit (VBENA)
1=Enabled, 0=Disabled
31:12 Not Used
5:0 Latched VME Address Modifier
31:6 Not Used
0x001
All Latched VME Address
Embedded PC/RTOS Features 41