Reset Function - NEC mPD75512 Datasheet

9.

RESET FUNCTION

When the RESET signal is input, the µ PD75512 is reset and each hardware is initialized as indicated in Table
9-1. Fig. 9-1 shows the reset operation timing.
RESET input
Operation mode
or standby mode
Hardware
Program Counter (PC)
PSW Carry Flag (CY)
Skip Flag (SK0-2)
Interrupt Status Flag (IST0, 1)
Bank Enable Flag (MBE, RBE)
Stack Pointer (SP)
Data Memory (RAM)
General-Purpose Register
(X, A, H, L, D, E, B, C)
Bank Selection Register (MBS, RBS)
Basic Interval Counter (BT)
Timer
Mode Register (BTM)
Timer/Event Counter (T0)
Counter
Modulo Register
(TMOD0)
Mode Register (TM0)
TOE0, TOUT F/F
Timer/Pulse Modulo Register
Generator
Mode Register
Watch Timer
Mode Register (WM)
*: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input.
34
Internal reset operation
Fig. 9-1 Reset Operation by RESET Input
Table 9-1 Status of Each Hardware after Reset (1/2)
RESET Input in Standby Mode
The contents of the lower 6 bits
of address 0000H of the program
memory are set to PC13-8, and
the contents of address 0001H
are set to PC7-0.
The contents of bit 6 of address
0000H of the program memory
are set to RBE and those of bit 7
are set to MBE.
Wait
(31.3ms/4.19MHz)
HALT mode Operation mode
RESET Input during Operation
Retained
0
0
Undefined
Retained *
Retained
0, 0
Undefined
0
0
FFH
0
0, 0
Retained
0
0
µ PD75512
Same as left
Undefined
0
0
Same as left
Undefined
Undefined
Undefined
0, 0
Undefined
0
0
FFH
0
0, 0
Retained
0
0