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6.5
WATCH TIMER
The µ PD75512 has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4.
• Sets the test flag (IRQW) with 0.5 sec interval.
The standby mode can be released by IRQW.
• 0.5 second interval can be generated either from the main system clock or subsystem clock.
• Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient
for program debugging, test, etc.
• Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock
frequency trimming.
• The frequency divider circuit can be cleared so that zero second watch start is possible.
f
X
128
From the
(32.768 kHz)
clock
f
generator
XT
(32.768 kHz)
WM
WM7
Remarks: ( ) is for f
6.6
TIMER/EVENT COUNTER
The µ PD75512 has a built-in 1-ch timer/event counter. The timer/event counter has these functions:
• Programmable interval timer operation
• Outputs square-wave signal of an arbitrary frequency to the PTO0 pin.
• Event counter operation
• Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation).
• Supplies serial shift clock to the serial interface circuit.
• Count condition read out function
f
W
Selector
Frequency divider
(32.768
kHz)
f
(2.048
W
16
kHz)
0
0
0
0
WM2 WM1 WM0
Bit test
8
instruction
Internal bus
= 4.194304 MHz, f
= 32.768 kHz.
X
XT
Fig. 6-4 Watch Timer Block Diagram
f
W
(256 Hz: 3.91 ms)
2
7
Selector
f
W
14
2
(2 Hz
0.5 sec)
Clear
Output buffer
PORT2.3
P23
Port 2
output
input/output
latch
mode
µ PD75512
INTW
(IRQW
set signal)
P23/BUZ
Bit 2 of PMGB
23
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