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6. DMA Controller (DMAC)
6.1. Overview
The main features of the DMAC are outlined below.
•
Supports byte, halfword, and word transfers.
•
Each DMAC channel can be configured to different transfer conditions independently.
•
Supports memory-to-memory, memory-to-peripheral circuit, and peripheral circuit-to-memory
transfers.
•
Supports hardware DMA requests from peripheral circuits and software DMA requests.
•
Priority level for each channel is selectable from two levels.
•
DMA transfers are allowed even if the CPU is placed into HALT mode. Figure 6.1.1 shows the
configuration of the DMAC.
Item
Number of channels
Transfer source memories
Transfer destination memories
Transfer source peripheral circuits
Transfer destination peripheral
circuits
DMAC
RMSETn
RMCLRn
CPU core
ENDIESETn
ENDIECLR
ERRIESET
ERRIECLR
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Table 6.1.1 DMAC Channel Configuration of S1C31D50
4 channels (Ch.0 to Ch.3)
Internal Flash memory, external Flash memory, RAM
RAM
UART3, SPIA, QSPI, I2C, T16B, ADC12A
UART3, SPIA, QSPI, I2C, T16B
MSTEN
Ch.n
CPTRn
DMA transfer
ENSETn
control circuit
ENCLRn
PASETn
PACLRn
PRSETn
PRCLRn
Interrupt
control circuit
Figure 6.1.1 DMAC Configuration
Seiko Epson Corporation
S1C31D50
CHNLS[4:0]
STATE[3:0]
MSTENSTA
ACPTRn
Bus matrix
SWREQn
Peripheral circuit
DMA transfer request
Peripheral circuit
DMA transfer request
ENDIFn
ERRIF
Flash memory,
RAM, etc.
6-1
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