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At start of data transmission
Standby state (SCL = low)
TXSTART = 1 1stAddr/W→TXD[7:0]
2
S
1stAddr/W
I
C bus
TXSTART = 0
STARTIF = 1
TBEIF = 1
At start of data transmission
Standby state (SCL = low)
TXSTART = 1 1stAddr/W→TXD[7:0]
S
1stAddr/W
I2C bus
TXSTART = 0
STARTIF = 1
TBEIF = 1
Figure 16.4.4.2 Example of Data Transfer Starting Operations in 10-bit Address Mode (Master Mode)
16.4.5. Data Transmission in Slave Mode
A data sending procedure in slave mode and the I2C Ch.n operations are shown below. Figures 16.4.5.1
and 16.4.5.2 show an operation example and a flowchart, respectively.
Data sending procedure
1. Wait for a START condition interrupt (I2C_nINTF.STARTIF bit = 1).
Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred.
2. Check to see if the I2C_nINTF.TR bit = 1 (transmission mode).
(Start a data receiving procedure if the I2C_nINTF.TR bit = 0.)
3. Write transmit data to the I2C_nTXD register.
4. Wait for a transmit buffer empty interrupt (I2C_nINTF.TBEIF bit = 1), a NACK reception interrupt
(I2C_nINTF.NACKIF bit = 1), or a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1).
i. Go to Step 3 when a transmit buffer empty interrupt has occurred.
ii. Go to Step 5 after clearing the I2C_nINTF.NACKIF bit when a NACK reception interrupt has
occurred.
iii. Go to Step 6 when a STOP condition interrupt has occurred.
5. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1) or a START condition interrupt
(I2C_nINTF.STARTIF bit = 1).
i. Go to Step 6 when a STOP condition interrupt has occurred.
ii. Go to Step 2 when a START condition interrupt has occurred.
6. Clear the I2C_nINTF.STOPIF bit and then terminate data sending operations.
Data sending operations
START condition detection and slave address check
While the I2C_nCTL.MODEN bit = 1 and the I2C_nCTL.MST bit = 0 (slave mode), the I2C Ch.n
monitors the I
C bus. When the I2C Ch.n detects a START condition, it starts receiving of the slave
2
address sent from the master. If the received address is matched with the own address set to the
I2C_nOADR.OADR[6:0] bits (when the I2C_nMOD.OADR10 bit = 0 (7-bit address mode)) or the
I2C_nOADR.OADR[9:0] bits (when the I2C_nMOD.OADR10 bit = 1 (10-bit address mode)), the
I2C_nINTF.STARTIF bit and the I2C_nINTF.BSY bit are both set to 1. The I2C Ch.n sets the I2C_nINTF.TR
16-12
2ndAddr→ TXD[7:0]
Data 1 → TXD[7:0]
A
2ndAddr
A
Data 1
TBEIF = 1
TBEIF = 1
2ndAddr→TXD[7:0]
TXSTART = 1
A
2ndAddr
A
Sr
TBEIF = 1
TBEIF = 1
TXSTART = 0
STARTIF = 1
TBEIF = 1
Software bit operations
Operations by I2C (master mode)
S: START condition, Sr: Repeated START condition, P: STOP condition,
A: ACK, A: NACK, 1stAddr/W: 1st address + W(0), 1stAddr/R: 1st address + R(1),
2ndAddr: 2nd address, Data n: 8-bit data
Seiko Epson Corporation
A
TBEIF = 1
1stAddr/R → TXD[7:0]
1stAddr/R
A
Data 1
A
RBFIF = 1
Hardware bit operations
Operations by the external slave
RXD[7:0]→ Data 1
Data 2
A
RBFIF = 1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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