Table of Contents
Advertisement
2.6
Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In the H8/3664 Series, the upper eight bits are ignored
in the generated 24-bit address, so the effective address is 16 bits.
2.6.1
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.9. Each instruction uses a
subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A, CPU Instruction Set. Arithmetic and logic instructions
can use the register direct and immediate modes. Data transfer instructions can use all addressing
modes except program-counter relative and memory indirect. Bit manipulation instructions use
register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and
register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing
mode to specify a bit number in the operand.
Table 2.9
Addressing Modes
No.
Addressing Mode
1
Register direct
2
Register indirect
3
Register indirect with displacement
4
Register indirect with post-increment
Register indirect with pre-decrement
5
Absolute address
6
Immediate
7
Program-counter relative
8
Memory indirect
Symbol
Rn
@ERn
@(d:16, ERn)/@(d:24, ERn)
@ERn+
@–ERn
@aa:8/@aa:16/@aa:24
#xx:8/#xx:16/#xx:32
@(d:8, PC)/@(d:16, PC)
@@aa:8
33
Advertisement
Table of Contents
