Epson S1C17001 Technical Manual page 66

Stabilization wait time at start of OSC3 oscillation
The OSC3 oscillator circuit incorporates an oscillation stabilization wait timer to prevent malfunctions due
to unstable clock operations at the start of OSC3 oscillation—for example, when power is first turned on, on
awaking from SLEEP, or when the OSC3 oscillation circuit is turned on via software. The OSC3 clock is not
fed to the system until the time set for this timer has elapsed.
Four different oscillation stabilization wait times can be selected using the OSC3WT[1:0] (D[5:4]/OSC_CTL
register)
∗ OSC3WT[1:0]: OSC3 Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[5:4]/0x5061)
This is set to 1,024 cycles (OSC3 clock) after initial resetting. The CPU does not begin operating immediately after
resetting until this time has elapsed.
Note: The OSC3 oscillation start time depends on the oscillator and externally connected compo-
nents. The time should be set with an adequate oscillation stabilization wait time. Refer to the
typical oscillation start times specified in "24 Electrical Characteristics."
S1C17001 TECHNICAL MANUAL
Table 7.2.2: OSC3 oscillation stabilization wait time settings
OSC3WT[1:0]
0x3
0x2
0x1
0x0
Oscillation stabilization
wait time
128 cycles
256 cycles
512 cycles
1,024 cycles
(Default: 0x0)
EPSON
7 OSCILLATOR CIRCUIT (OSC)
57