0X4226/0X4246/0X4266: 16-Bit Timer Ch.x Control Registers (T16_Ctlx) - Epson S1C17001 Technical Manual

0x4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (T16_CTLx)

Register name Address Bit
16-bit Timer 0x4226 D15–11 –
Ch.x Control 0x4246
D10
Register 0x4266
D9–8 CKSL[1:0]
(T16_CTLx) (16 bits)
D7–5 –
D4
D3–2 –
D1
D0
Note: The "x" in the register names indicates the channel number (0 to 2).
0x4226: 16-bit Timer Ch.0 Control Register (T16_CTL0)
0x4246: 16-bit Timer Ch.1 Control Register (T16_CTL1)
0x4266: 16-bit Timer Ch.2 Control Register (T16_CTL2)
D[15:11] Reserved
D10 CKACTV: External Clock Active Level Select Bit
Selects the external input pulse polarity or external clock counting edge.
1 (R/W): Active High/Rising edge (default)
0 (R/W): Active Low/Falling edge
This setting determines whether the external input clock rising edge or falling edge is used for counting
in external clock mode (when CKSL[1:0] = 0x1). In pulse width measurement mode (when CKSL[1:0]
= 0x2), this setting determines external input pulse polarity.
D[9:8] CKSL[1:0]: Input Clock and Pulse Width Measurement Mode Select Bits
Select the 16-bit timer operating mode.
Internal clock mode uses the prescaler output clock as the count clock. The timer counts down from
the initial value set in the reload data register and outputs an underflow signal when the counter under-
flows. The underflow signal is used to generate an interrupt and an internal serial interface clock. The
time until underflow occurs can be finely programmed by selecting the prescaler clock and initial coun-
ter value, allowing its use for serial transfer clock generation and sporadic time measurement.
External clock mode uses the clock and pulses input via the input/output ports (Ch.0: P16, Ch.1: P07,
Ch.2: P06) as a count clock and can also be used as an event counter. Timer operations other than the
input clock are the same as for internal clock mode.
In pulse width measurement mode, when pulses with the specified polarity are input from the external
clock port, the internal clock is fed only while the signal is active, enabling counting. This enables inter-
rupt generation and input pulse width measurements for pulse inputs of the specified width or greater.
D[7:5] Reserved
S1C17001 TECHNICAL MANUAL
Name Function
reserved
CKACTV External clock active level select
Input clock and pulse width
measurement mode select
reserved
TRMD Count mode select
reserved
PRESER Timer reset
PRUN Timer run/stop control
Table 11.9.3: Operating mode selection
CKSL[1:0]
0x3
0x2 Pulse width measurement mode
0x1
0x0
EPSON
Setting
–
1 High 0 Low
CKSL[1:0] Mode
0x3 reserved
0x2 Pulse width
0x1 External clock
0x0 Internal clock
–
1 One shot 0 Repeat
–
1 Reset 0 Ignored
1 Run 0 Stop
Operating mode
Reserved
External clock mode
Internal clock mode
(Default: 0x0)
11 16-BIT TIMER (T16)
Init. R/W Remarks
– – 0 when being read.
1 R/W
0x0 R/W
– – 0 when being read.
0 R/W
– – 0 when being read.
0 W
0 R/W
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