Mitsubishi Electric Q26UD(E)HCPU User Manual page 555

Number Name Meaning
SD781
to
SD785
Mask pattern
of IMASK Mask pattern
instruction
SD781
to
SD793
SD794
PID limit
0: With limit
setting (for
1: Without
incomplete
limit
derivative)
SD794
to
SD795
Explanation
The mask patterns masked by the IMASK instruction are
stored as follows.
b15
l63 l49
SD781 to
l79
SD782 to l65
to to
l127 l113
SD785 to
The mask patterns masked by the IMASK instruction are
*1
stored as follows.
b15
l63 l49
SD781 to
SD782 l79 to l65
to
l255 l241
SD793 to
*1: The Q00UJCPU, Q00UCPU, and Q01UCPU cannot
use SD786 to SD793.
This register stores the limit of each PID loop as shown
below.
to
b15 b8 b7
SD794 Loop8
This register stores the limit of each PID loop as shown
below.
b15 to
SD794 Loop16 to
SD795 Loop32 to
Set by
(When
Set)
b1 b0
l48
l64
l112
S (During
execution)
b1 b0
l48
l64
l240
to
b1 b0
to Loop2 Loop1
U
b1 b0
Loop2 Loop1
Loop18 Loop17
APPENDICES
Corresponding
Corresponding
ACPU
CPU
D9
Q00J/Q00/Q01
New
Qn(H)
QnPH
QnPRH
QnU
LCPU
Q00J/Q00
*1
/Q01
New
*4
Qn(H)
QnPRH
QnU
LCPU
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