Casio TE-2000 Service Manual page 20

5-3. GATE ARRAY (IC15)
Pin description
PIN NO PIN NAME I / O
1 Vcc
2 MTR_1R
3 MTR_2R
4 MTR_3R
5 MTR_4R
6 STB_R1
7 STB_R2
8 STB_R3
9 STB_R4
10 STB_R5
11 STB_R6
12 GND
13 H_DAT
14 H_CLK
15 MT_IRQ
16 CK1.25M
17 GA_TEST 'TEB)
18 RESET
19 RD
20 Vcc
21 GND
22 WR
23 ASTB
24 RAM_Dis
25 A15
26 A14
27 A13
28 A12
29 A11
30 A10
31 A9
32 A8
33 AD7
34 AD6
35 AD5
36 AD4
37 AD3
38 AD2
39 AD1
40 Vcc
41 GND
42 GND
43 ADO
44 SMA
45 SIN
46 SOUT
47 A7
48 GND
49 A6
50 A5
D E S C R I P T I O N
- VCC
O MTR_R1 by Printer circuit
O MTR_R2 by Printer circuit
O MTR_R3 by Printer circuit
O MTR_R4 by Printer circuit
O STB_R1 by Printer
O STB_R2 by Printer
O STB_R3 by Printer
O STB_R4 by Printer
O STB_R5 by Printer
O STB_R6 by Printer
- Vss
O DI signa by Printer
O CLK signal by Printer
O MT_IRQ (to CPU)
I CLOCK (to CPU)
I Vss
I RESET signal
I Read signal for Memory
- VCC
- Vss
I Write signal for Memoey
I ASTB (from CPU)
I Chip select for RAM
I ADDRESS (A15)
I ADDRESS (A14)
I ADDRESS (A13)
I ADDRESS (A12)
I ADDRESS (A11)
I ADDRESS (A10)
I ADDRESS (A9)
I ADDRESS (A8)
I/O DATA BUS (AD7)
I/O DATA BUS (AD6)
I/O DATA BUS (AD5)
I/O DATA BUS (AD4)
I/O DATA BUS (AD3)
I/O DATA BUS (AD2)
I/O DATA BUS (AD1)
- Vcc
- Vss
- Vss
I/O DATA BUS (AD0)
I CP4 terminal
I CP5 terminal
O CP6 terminal
O ADDRESS (A7)
- Vss
O ADDRESS (A6)
O ADDRESS (A5)
— 18 —
PIN NO PIN NAME I / O
51 A4
52 A3
53 A2
54 A1
55 A0
56 GND
57 Vcc
58 BA20
59 BA19
60 GND
61 BA18
62 BA17
63 BA16
64 BA15
65 BA14
66 BA13
67 BA12
68 GND
69 Vcc
70 BA11
71 ROM_CE
72 GND
73 RAM1_CE
74 RAM2_CE
75 FIS_CE
76 STP_CE
77 FLH_CE
78 Vcc
79 GND
80 GND
81 Vcc
82 KI1
83 KI2
84 KI3
85 KI4
86 KI5
87 KI6
88 KI7
89 KI8
90 S1A (KC_1)
91 S1B (KC_2)
92 S1C (KC_3)
93 S1D (KC_4)
94 S1E (KC_5)
95 S1F (KC_6)
96 S1G (KC_7)
97 A1DP (KC_8)
98 S2A (KC_9)
99 S2B (KC_10)
100 Vcc
D E S C R I P T I O N
O ADDRESS (A4)
O ADDRESS (A3)
O ADDRESS (A2)
O ADDRESS (A1)
O ADDRESS (A0)
- Vss
- VDD
- Not used
O ADDRESS (A19)
- Vcc
O ADDRESS (A18)
O ADDRESS (A17)
O ADDRESS (A16)
O ADDRESS (A15)
O ADDRESS (A14)
O ADDRESS (A13)
O ADDRESS (A12)
- Vss
- VCC
O ADDRESS (A11)
O Chip enable for ROM
- Vss
O Chip enable for RAM1
O Chip enable for RAM2
O Chip enable for FIS ROM
O Chip enable for RAM
O Chip enable for FLASH ROM
- VCC
- Vss
- Vss
- VCC
I KEY in signal
I KEY in signal
I KEY in signal
I KEY in signal
I KEY in signal
I KEY in signal
I KEY in signal
I KEY in signal
O KEY scan signal
O KEY scan signal
O KEY scan signal
O KEY scan signal
O KEY scan signal
O KEY scan signal
O KEY scan signal
O KEY scan signal
O KEY scan signal
O KEY scan signal
- VCC