Philips 19PFL5522D Service Manual page 82

EN 82 9. LC7.2E LB
9.5 DVB-T Signal Processing
The DVB-T cell on the SSB is built around the "MOJO" MPEG
decoder PNX8314HS (item 7G00) and receives the signal from
the COFDM Channel Decoder TDA10046 (item 7F01). The
(hybrid) tuner TD1316AF (item 1101) supports digital (DVB-T)
reception and transports the signal via the VIM_IBO and
VIP_IBO lines. The digital data stream exits the DVB-T cell
when it is fed to the Trident SVP CX32 Video Processor (item
7202). A Common Interface (CI) slot allows reception of
encoded signals when used with a Conditional Access Module
(CAM) in combination with a smart card. See figure "Block
diagram DVB-T reception" for details.
1V2_MOJO
1V8S_SW
3V3_MOJO
4MHz CLK
RF_AGC_IBO
TDA10046
CI SLOT Channel
(STV0700) Decoder
TDA_SDA
LPF
TXD0
MOJO
RXD0
I 2 S (SD, WS, SCLK)
LC07 EU DVB Cell
Figure 9-5 Block diagram DVB-T reception
9.5.1 Common Interface (CI)
Introduction
The digital sets of this chassis are provided with a special slot
called Common Interface (CI). Together with a Conditional
Access Module (CAM) and a smart card, it is possible to
receive scrambled TV programs. This means that it is not
necessary to have a separate Set Top Box to receive digital
cable SDTV and HDTV programs (however this still is
possible).
The removable smart card, distributed by cable companies,
allows you to tune digital and high definition scrambled or
encrypted cable channels through the cable antenna. The
smart card is also required to receive premium digital TV
channels and services (where available) through the cable. A
smart card functionality includes conditional access and copy
protection.
Implementation
1. The receiver receives the digital data stream.
2. The data flows into the Conditional Access Module, which
contains the content provider's unscrambling algorithms.
3. This module verifies the existence of a smart card that
contains the subscriber's authorization code.
4. If the authorization code is accepted, the CAM
unscrambles the data and returns the data to the receiver
(if the code is not accepted, the data remains scrambled,
restricting access).
5. The receiver then decodes the data and outputs it for
viewing.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
SDA
HYBRID
MUX
SCL
TUNER
IF_AGC_IBO
VIP_IBO
VIM_IBO
TDA_SCL
IBO_R,G,B
IBO_CVBS
IBO_I 2 C_SD
IBO_I 2 C_SCL
IBO_IRQ
TRIDENT/uP
RESET_n
FLASH
SDRAM
Multi
Sound
Processor
9.5.2 Supply
The internal voltages that are used are:
• 5 V (+5V_SW)
• 3.3 V (+3V3_MOJO)
• 1.2 V (+1V2_MOJO)
• 1.8 V (+1V8S_SW).
During start-up, it is important that the +1V8S_SW line comes
up earlier than the +3V3_MOJO line. In order to implement this,
a delay circuit is added which is shown in figure "Delay
circuitry".
DVB_SW
I 2 C_SDA
I 2 C_SCL
Item 7J05 switches the MOSFET "on" and "off" (item 7J04).
The diode (item 6J03) performs a short-circuit protection for the
+3V3 output stage.
9.6 Video Processing
The video processing is completely handled by the Trident SVP
CX32 video processor which features:
SCART 2
• CVBS-input for analogue signals.
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• RGB-input for digital (DVB-T) signals.
• Motion and "edge-adaptive" de-interlacing.
• Integrated ADC.
• Built-in 8-bit LVDS transmitter.
• Colour stretch.
• Skin colour enhancement.
• 3D Digital Comb Video Decoder.
• Interlaced and Progressive Scan refresh.
• TeleText decoding.
• OSD and VBI/Closed Caption.
9.6.1 Video Application
S C A R T 1
S C A R T 2
S ID E A V
O n b o a rd E X T 3
E X T 4
H D M I2
H D M I1
Figure 9-7 Block diagram video processing
Figure 9-6 Delay circuitry
A n a lo g u e
C V B S _ R F
C V B S 1
F ro n t E n d
S C 1 _ R _ IN
P R _ R 2
S C 1 _ G _ IN
Y _ G 2
S C 1 _ B _ IN
P B _ B 2
S C 1 _ C V B S _ IN
P B _ B 3
S C 1 _ F B L _ IN
F B 1
C V B S _ O U T 1
S C 2 _ Y _ C V B S _ IN
P R _ R 3
S C 2 _ C _ IN
F S 2
F R O N T _ Y _ C V B S _ IN _ T
Y _ G 3
F R O N T _ C _ IN _ T
C
T r id e n t
Video Processor
SVP CX32
H D _ Y _ IN
Y _ G 1
H D _ P B _ IN
P B _ B 1
C V B S _ O U T 2
H D _ P R _ IN
P R _ R 1
IB O _ R _ IN
P C _ R
D i g F r o n t E n d
IB O _ G _ IN
P C _ G
( D V B-T
IB O _ B _ IN
d e m o d u la to r P C _ B
IB O _ C V B S _ IN
a n d d e c o d e r)
F S 1
H D M I_ Y (0 :7 )
H D M I_ C b (0 :7 )
H D M I_ C r (0 :7 )
H D M I
D e c o d e r
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C V B S
SCART 1 Mon. out
C V B S
SCART 2 Mon. out
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