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PIN No.
Symbol
Pin Name
Phase comparator
53
DO1/OT1/P
/output port
54
DO2/OT2/N
/Tin
/Tr. Input for LPF
55
P9-0/Tout
/Tr. Output for LPF
56
MUTE/P9-1
/Mute output
57
P9-2/DDCK2
/Clock output 2 for
/TEST
/TEST mode input
Function and Operation
PLL phase comparator output pins.
Tristate output: When the program counter
divider output is higher than the reference
frequency, High level is output; when the
output is lower, Low level; and when they
match, high impedance.
The doubler voltage V
comparator power supply. The V
supply potential is output for High level.
The DO1 and DO2 pins incorporate 3
types of output resistance (5 kΩ, 50 kΩ,
100 kΩ), which can be changed for each
pin.
output
The DO2 pin can change output resistance
automatically according to the phase
/P output
difference of the PLL. Therefore, lock-up
time is improved.
The DO2 pin can be programmed to
high-impedance or as an output port (OT1,
OT2). The phase comparator charge pump
control signal (P/N), which is used to
configure an external charge pump, can be
output from the DO1/2 pin.
If the phase comparator charge pump
control signal (P/N) is set, when the
program counter divider output is higher
than the reference frequency, P/N is
output at H/L level; when the output is
lower, L/H level; and when they match, L/L
level.
Pins P9-1 to P9-2 is 2-bit CMOS I/O ports.
The P9-0 pin is a 1-bit N-ch open-drain
I/O, allowing input and output to be
programmed in 1-bit units.
The P9-1 pin is used as the MUTE output.
The MUTE output is usually used for
muting control signal output. The MUTE bit
can be set to "1" through change in the
I/O port 9
input of the I/O port input release (BRK)
pin. The MUTE output logic can be set
through programming.
During system reset (
P9-2 pin is pulled down and becomes the
test mode input.
doubler
Therefore, the pin is normally used at Low
level or in open state during the reset
condition.
Through programming, it is possible to use
the N-ch FET transistor for low path filter
amplifiers (5.5 V voltage).
As for FET transistors, Tin pin is set as
gate input and Tout pin is set as drain
output.
11
is used for phase
DB
power
DB
(DO1/OT1/P, DO2/OT2)
T
in
T
out
Note: T
= "L"), the
RESET
TC9349AFG
Remarks
V
DB
R
out1
V
DB
R
out1~4
(T
, T
)
in
out
/T
setting
in
out
V
DD
Input instruction
(P9-0)
V
DD
V
DD
Input instruction
(MUTE/P9-1)
V
DD
V
DD
Input instruction,
Reset
(P9-2/DDCK2/TEST)
2006-02-24
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