Parallel Jtag Host Target Interface And Jtag - Motorola DSP56F801 Hardware User Manual

Evaluation module
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5
D
P O R T _ I DENT
P2
1
1 4
2
1 5
3
1 6
4
1 7
5
1 8
6
1 9
7
2 0
8
2 1
9
2 2
1 0
C
2 3
1 1
2 4
1 2
2 5
1 3
DB25M
+3.3V
B
R 4 3
P_RESET
5.1K
R 4 4
47K
A
5
Figure A-5. PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR
4
Parallel JTAG Interface
R 3 1
270
R 3 2
270
P O RT_RESET
R 3 3
PORT_TMS
270
P O RT_TCK
R 3 4
P O R T _ TDI
/ P O RT_TRST
270
P O R T _DE
R 3 5
270
P O R T _ VCC
R 3 7
P O RT_TDO
5 1 O h m
R 3 8
P O R T _ C O N NECT
5 1 O h m
U 1 0A
R 4 0
/ J _ R E SET
1
5.1K
2
/ P O R
/ J _ R E SET
74AC00
U 1 0 C
Q1
9
2N2222A
/J_TRST
1 0
74AC00
4
3
U 5
2
1 A 1
4
1 A 2
6
1 A 3
8
1 A 4
1 1
2 A 1
7
2 Y 2
5
2 Y 3
3
T1
1
2 Y 4
+ 3 .3V
2 0
V C C
1
1 G
1 9
2 G
J G 5
R 3 9
MC74LCX244D W
5.1K
On-Board
Host Target Interface
Disable
U 1 0B
4
3
6
/ R E S ET
5
7 4 AC00
U 1 0 D
1 2
8
1 1
/TRST
1 3
7 4 AC00
+3.3V
R 4 1
TDO
47K
R 4 2
/J_TRST
Title
PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR
47K
Document
Size
Number
B
Date:
Thursday, December 07, 2000
3
2
1
P_RESET
1 8
1 Y 1
TMS
1 6
1 Y 2
T C K
1 4
1 Y 3
TDI
1 2
1 Y 4
/J_TRST
9
2 Y 1
T D O
1 3
2 A 2
1 5
+3.3V
2 A 3
R 3 6
1 7
2 A 4
5.1K
1 0
G N D
+ 3 .3V
J 8
/J_TRST
1 3
1 4
1 1
1 2
/ J _ R E SET
9
1 0
TMS
7
8
KEY
TCK
5
6
T D O
3
4
TDI
1
2
JTAG Connector
DSP Standard Products Division
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
DSP56F801EVM.DSN
Designer:
Sheet
DSPD Design
2
1
D
C
B
A
FAX: (480) 413-2510
Rev.
1.0
5
of
11

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