Sleep Mode; Pseudo-Watch Mode - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

6.4 Operations

6.4.1 Sleep mode

Transition to sleep mode
The standby control circuit is set to sleep mode by writing a "1" to the SLP bit, a "1' to the TMD bit, and a
"0" to the STP bit in the low power consumption mode control register. In sleep mode, only the clock sup-
plied to the CPU is stopped; in this mode, the CPU stops, but the peripheral circuits continue to operate.
If an interrupt request is generated when the "1" is written to the SLP bit, the standby control circuit does
not go into sleep mode. In this case, if the CPU is not accepting interrupts, the next instruction is executed;
if the CPU is accepting interrupts, processing branches immediately to the interrupt processing routine.
The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are
maintained in sleep mode.
Releasing sleep mode
The standby control circuit is used for wake-up from sleep mode when a reset signal is input or when an
interrupt is generated. If a wake-up from sleep mode was done by a reset source, the device enters the
reset state after wake-up from sleep mode is completed.
If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in
sleep mode, the standby control circuit is used for wake-up from sleep mode. Once wake-up from sleep
mode is completed, the interrupt is handled in the normal manner. If the settings of the I flag, ILM bits, and
the interrupt control register (ICR) are all set so that the interrupt is accepted, then the CPU executes inter-
rupt processing. If the settings do not permit the interrupt to be accepted, then processing resumes from
the instruction that follows the instruction that put the device into sleep mode.

6.4.2 Pseudo-watch mode

Transition to pseudo-watch mode
The standby control circuit is set to pseudo-watch mode by writing a "1" to the SCS bit and a "0" to the
MCS bit in the clock selection register, and a "1" to the TMD bit and a "1" to the STP bit in the low power
consumption mode control register.
oscillation (main and sub), the watch timer, and the timebase timer. Practically all chip functions cease.
In addition, the SPL bit in the low power consumption mode control register can be used to control whether
I/O pins maintain their previous states or go to high impedance state in pseudo-watch mode.
If an interrupt request is generated when the "1" is written to the STP bit, the standby control circuit does
not shift to pseudo-watch mode.
The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are hold in
pseudo-watch mode.
Exit from pseudo-watch mode
The standby control circuit is used for exit from pseudo-watch mode when a reset signal is input or when
an interrupt is generated. If an exit from pseudo-watch mode was performed by a reset source, the device
enters the reset state after exit from pseudo-watch mode.
When recovering from pseudo-watch mode, the standby control circuit is activated first for exit from
pseudo-watch mode, and then begins waiting for the PLL clock oscillation stabilization wait time to elapse.
Therefore, even if the exit from of pseudo-watch mode is due to a reset source, the main clock is used for
the reset sequence.
If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in
pseudo-watch mode, the standby control circuit is activated for exit from pseudo-watch mode. Once exit
from pseudo-watch mode is completed, the interrupt is handled in the normal manner. If the settings of the
I flag, ILM bits, and the interrupt control register (ICR) are all set so that the interrupt is accepted, then the
CPU executes interrupt processing. If the settings do not permit the interrupt to be accepted, then
68 Chapter 6: Low Power Control Circuit
In pseudo-watch mode, all clocks stop, except for the source
MB90580 Series