12.3 Register and Register Details
12.3.3
Serial Input Data Register (SIDR0/1/2/3/4)/ Serial Ouput Data Register (SODR0/1/2/3/4)
Serial input register/Serial output register
Address : 000022
000026
00002A
000084
00008A
Read/write
Initial value
These registers are data buffer registers for transmission and reception.
When a data item is seven bits long, the high-order one bit (D7) is invalid. To write a data item in the SODR
register, ensure that '1' is written to TDRE of the SSR register.
Note: Writing a data item at this address means to write it to the SODR register. Reading this
address means to read the SIDR register.
12.3.4 Serial Status Register (SSR0/1/2/3/4)
Serial input register/Serial output register
Address : 000022
000026
00002A
000084
00008A
Read/write
Initial value
The SSR register consists of the flags indicating the UART operation.
[bit 15] PE (Parity error)
This interrupt request flag is set when a parity error occurs during reception.
To clear a set flag, write '0' to the REC bit (bit 10) of the SCR register.
When this bit is set, the data in SIDR is invalid.
0
No parity error has occurred.
A parity error has occurred.
1
[bit 14] ORE (Overrun error):
This interrupt request flag is set when an overrun error occurs during reception.
To clear a set flag, write '0' to the REC bit (bit 10) of the SCR register.
When this bit is set, the data in SIDR is invalid.
No overrun error has occurred.
0
An overrun error has occurred.
1
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Chapter 12: UART
H
7
6
H
H
D7
D6
H
H
(R/W)
(R/W)
(R/W)
(X)
(X)
H
7
6
H
H
D7
D6
H
H
(R/W)
(R/W)
(R/W)
(X)
(X)
5
4
3
D5
D4
D3
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
5
4
3
D5
D4
D3
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
2
1
0
SIDR0/SODR0
D2
D1
D0
SIDR1/SODR1
SIDR2/SODR2
SIDR3/SODR3
(R/W)
(R/W)
SIDR4/SODR4
(X)
(X)
(X)
2
1
0
SIDR0/SODR0
D2
D1
D0
SIDR1/SODR1
SIDR2/SODR2
SIDR3/SODR3
(R/W)
(R/W)
SIDR4/SODR4
(X)
(X)
(X)
[initial value]
[initial value]
Bit number
Bit number
MB90580 Series