Sony CXD5602 User Manual page 896

3.13.3.2 Clock Reset Generator
The following shows the clock system diagram.
RCOSC
XOSC
SYSPLL
RTC_CLK_IN
(32.768kHz)
1/2
1/3
1/4
1/5
APP_CKSEL.APP_PLL_DIV5
APP_CKSEL.STAT_SP_CLK_SEL4
APP_CKSEL.STAT_APP_CLK_SEL4
APP_CKEN.APP
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
APP_CKEN.AHB
P1x_00(MCLK)
APP_DIV.AU_MCLK
APP_CKSEL.AU_MCK
APP_CKEN.MCLK
0
0
1
1
2
2
3
3
0
1
0
0
ck_cpu_bus
1
1
2
1/M
2
3
3
0
1
0
1/M
1
2
3
Reserved
Figure APP-102 Application Domain Clock System
－896/1010－
CK CK_APP
GATE
GEAR_AHB
CK_GATE_AHB.ck_gate_dsp0-5
ck_ahb_gear
1/M
CK_APP_AHB
CK
GATE
CK_GATE_AHB.ck_gate_aud
CK_APP_MCLK
CK_GATE_AHB.ck_gate_dmac
CK_GATE_AHB.ck_gate_sake
CK_GATE_AHB.ck_gate_kaki
CK
GATE
CK_GATE_AHB.ck_gate_img
GEAR_IMG_UART.gear_m_uart
GEAR_IMG_UART.gear_n_uart
GEAR_IMG_SPI.gear_m_spi
GEAR_IMG_SPI.gear_n_spi
GEAR_IMG_WSPI.gear_m_wspi
GEAR_IMG_WSPI.gear_n_wspi
GEAR_M_IMG_VENB
GEAR_N_IMG_VENB
CK_GATE_AHB.ck_gate_mmc
CK_GATE_AHB.ck_gate_sdio
GEAR_PER_SDIO.gear_m_sdio
GEAR_PER_SDIO.gear_n_sdio
CK_GATE_AHB.ck_gate_usb
GEAR_PER_USB.gear_n_usb
GEAR_PER_USB.gear_n_usb
CXD5602 User Manual
N/M
ADSP
CK
CK
CK
GATE
CK
GATE
CK
GATE
CK
GATE
GATE
GATE
AUDIO
CK
CLK_AHB
GATE
MCLK
ADMAC
CK
HCLK
GATE
Crypto
CK
GATE
CK
GATE
CIS I/F
CK
CLK_AHB/APB
GATE
2D Graphics
IMG_CLK_AHB
UART
1/M
PCLK
CK
UARTCLK
GATE
SPI4
1/M
PCLK
CK
SSPCLK
GATE
SPI5
1/M
PCLK
CK
SSPCLK
GATE
IDMAC
HCLK
Pulse w idth
N/M
VideoTG
co nversio n
CK
eMMC
GATE
MMC_I_HCLK
CK
SDIO
GATE
HCLK
1/M
CK
CLK_IN
GATE
CK
USB
GATE
USBD_SYS_CLK_I
1/M
CK
1/2
USBD_CLK_32K_I
GATE