Sony CXD5602 User Manual page 881

3.10.4.3 Clock Supply Start and Stop
3.10.4.3.1 Clock Supply Start
Perform the following control to start supplying the SSPCLK clock and PCLK clock to the SPI4.
1. Reset release
PWD_RESET0.PWD_APP=1'b1
RESET.xrs_img=1'b1
2. Supply the CK_APP (For details, refer to the APP Section (3.13))
3. Clock supply for the SPI4 register and division ratio setting
GEAR_AHB.gear_m_ahb=(arbitrary: denominator setting of the division ratio)
GEAR_AHB.gear_n_ahb=(arbitrary: numerator setting of the division ratio)
CK_GATE_AHB.ck_gate_img=1'b1
4. SPI4 control clock supply and division ratio setting
GEAR_IMG_SPI.gear_m_spi=(arbitrary: denominator setting of the division ratio)
GEAR_IMG_SPI.gear_n_spi=1'b1
3.10.4.3.2 Clock Supply Stop
Perform the following control to stop supplying the SSPCLK clock and PCLK clock to the SPI4.
1. SPI4 control clock stop
GEAR_IMG_SPI.gear_n_spi=1'b0
2. SPI4 register's clock stop
CK_GATE_AHB.ck_gate_img=1'b0
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CXD5602 User Manual