Hitachi H8S/2633 Hardware Manual page 339

In repeat mode, one operation transfers one byte or one word of data.

From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the

initial state of the transfer counter and the address register specified as the repeat area is restored,

and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and

therefore CPU interrupts cannot be requested when DISEL = 0.

Table 9-6 lists the register information in repeat mode and figure 9-7 shows memory mapping in

repeat mode.

DTC source address register

DTC destination address register

DTC transfer count register AH

DTC transfer count register AL

DTC transfer count register B

Abbreviation

Figure 9-7 Memory Mapping in Repeat Mode

Designates source address

Designates destination address

Holds number of transfers

Designates transfer count