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2.9.1
Overview............................................................................................................... 63
2.9.2
On-Chip Memory (ROM, RAM).......................................................................... 63
2.9.3
On-Chip Supporting Module Access Timing ....................................................... 65
2.9.4
External Address Space Access Timing ............................................................... 66
2.10 Usage Note ......................................................................................................................... 66
2.10.1 TAS Instruction .................................................................................................... 66
Section 3
MCU Operating Modes
3.1
Overview............................................................................................................................ 67
3.1.1
Operating Mode Selection .................................................................................... 67
3.1.2
Register Configuration.......................................................................................... 68
3.2
Register Descriptions ......................................................................................................... 68
3.2.1
Mode Control Register (MDCR) .......................................................................... 68
3.2.2
System Control Register (SYSCR)....................................................................... 69
3.2.3
Pin Function Control Register (PFCR) ................................................................. 71
3.3
Operating Mode Descriptions............................................................................................ 74
3.3.1
Mode 4 .................................................................................................................. 74
3.3.2
Mode 5 ................................................................................................................. 74
3.3.3
Mode 6 .................................................................................................................. 74
3.3.4
Mode 7 .................................................................................................................. 74
3.4
Pin Functions in Each Operating Mode ............................................................................. 75
3.5
Address Map in Each Operating Mode.............................................................................. 75
Section 4
Exception Handling
4.1
Overview............................................................................................................................ 79
4.1.1
Exception Handling Types and Priority................................................................ 79
4.1.2
Exception Handling Operation ............................................................................. 80
4.1.3
Exception Vector Table ........................................................................................ 80
4.2
Reset................................................................................................................................... 82
4.2.1
Overview............................................................................................................... 82
4.2.2
Types of Reset ...................................................................................................... 82
4.2.3
Reset Sequence ..................................................................................................... 83
4.2.4
Interrupts after Reset............................................................................................. 85
4.2.5
State of On-Chip Supporting Modules after Reset Release.................................. 85
4.3
Traces ................................................................................................................................. 86
4.4
Interrupts ............................................................................................................................ 87
4.5
Trap Instruction.................................................................................................................. 88
4.6
Stack Status after Exception Handling .............................................................................. 89
4.7
Notes on Use of the Stack.................................................................................................. 90
Section 5
Interrupt Controller
5.1
Overview............................................................................................................................ 91
5.1.1
Features ................................................................................................................. 91
5.1.2
Block Diagram...................................................................................................... 92
ii
................................................................................. 67
........................................................................................ 79
......................................................................................... 91
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