Fujitsu F2MC-8FX Hardware Manual page 398

F2mc-8fx 8-bit microcontroller
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2
CHAPTER 22 I
C
2
Table 22.5-2 I
C Bus Control Register 1 (IBCR10) (2 / 2)
Bit name
INT:
Transfer completion
bit0
interrupt request flag
bit
Note:
384
This bit is used to detect transfer completion.
• A transfer completion interrupt request is generated if this bit and the IBCR10:INTE bit are both
"1".
• This bit is set to "1" upon completion of transfer of 1-byte address or data (whether or not this
includes an acknowledgment depends on the IBCR00:INTS setting) if any of the following four
conditions is satisfied.
- In bus master mode
- Addressed as slave
- General call address received
- Arbitration lost detected
• This bit is set to "0" in the following cases:
- "0" written to the bit
- Repeated start condition (IBCR10:SCC = 1) or stop condition (IBCR10:MSS = 0) occurred in
master mode.
• An attempt to write "1" to this bit leaves its value unchanged and has no effect on the operation.
• The bit returns "1" when read by a read-modify-write operation.
• The SCL0 line remains at "L" while this bit is "1".
• Writing "0" to clear the bit (change the value to "0") releases the SCL0 line to enable transmission
for the next byte of data.
Note:
• If "1" is written to IBCR10:SCC when this bit is "0", the IBCR10:SCC bit has priority
and the start condition is generated.
• If "0" is written to IBCR10:MSS when this bit is "0", the IBCR10:MSS bit has priority
and the stop condition is generated.
• If IBCR00:INTS = 1 when data is received, this bit is set to "1" upon completion of
transfer of one-byte data (including no acknowledgment). In other cases, this bit is set to
"1" upon completion of transmission or reception of one-byte data/address including an
acknowledgment.
When clearing the interrupt request flag (IBCR10:BER) by writing "0", do not update the
interrupt request enable bit (IBCR10:BEIE) at the same time.
All the bits in IBCR10 except the BER and BEIE bits are cleared to "0" either when operation is
disabled (ICCR:EN = 0) or when a bus error occurs (IBSR0:BER = 1).
Function

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