Operations Of Port 9 - Fujitsu F2MC-8FX Hardware Manual

9.7.2

Operations of Port 9

This section describes the operations of port 9.
Operations of Port 9
Operation as an output port
• Setting the corresponding DDR bit to "1" sets a pin as an output port.
• For a peripheral function sharing pins, disable its output.
• When a pin is set as an output port, it outputs the value of the PDR to pins.
• If data is written to the PDR, the value is stored in the output latch and output to the pin as it is.
• Reading the PDR returns the PDR value.
Operation as an input port
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for LCD as an input port, set the V1 to V3 selection bits (VE2/VE1) ofthe
LCDC enable register (LCDCE1) to "0".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-
write commands, the value of the PDR register is read.
Operation as a peripheral function output
• Setting the output enable bit of a peripheral function sets the corresponding pin as a peripheral function
output.
• The pin value can be read from the PDR register even if the peripheral function output is enabled.
Therefore, the output value of a peripheral function can be read by the read operation on PDR register.
However, the read-modify-write command returns the PDR value.
Operation at reset
• For P92 to P90, resetting the CPU initializes the DDR values to "0" and the VE2/VE1 bits in LCDCE1
to "1", and port input disabled.
• For P95 and P94, resetting the CPU initializes the DDR values to "0", and sets the port input enabled.
Operation in stop mode and watch mode
• If the pin state specification bit in the standby control register (STBC:SPL) is set to "1" when the device
switches to stop or watch mode, the pin is set forcibly to the high-impedance state regardless of the
DDR value. Note that the input is locked to "L" and blocked in order to prevent leaks due to freed input.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O and the
output is maintained.
Operation of the pull-up register
• Writing "1" to the PUL internally connects the pull-up register to the pin. When the output is "L" level,
the pull-up register is disconnected regardless of the PUL value.
CHAPTER 9 I/O PORT
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