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Register name
Address
Bit
Areas 14–13
0048122
DF–9
set-up register
(HW)
D8
D7
D6
D5
D4
D3
D2
D1
D0
Areas 8–7
0048128
DF–9
set-up register
(HW)
D8
D7
D6
D5
D4
D3
D2
D1
D0
Areas 6–4
004812A
DF–E
set-up register
(HW)
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1C33L03 FUNCTION PART
Name
Function
–
reserved
A14DRA
Area 14 DRAM selection
A13DRA
Area 13 DRAM selection
A14SZ
Areas 14–13 device size selection
A14DF1
Areas 14–13
A14DF0
output disable delay time
–
reserved
A14WT2
Areas 14–13 wait control
A14WT1
A14WT0
–
reserved
A8DRA
Area 8 DRAM selection
A7DRA
Area 7 DRAM selection
A8SZ
Areas 8–7 device size selection
A8DF1
Areas 8–7
A8DF0
output disable delay time
–
reserved
A8WT2
Areas 8–7 wait control
A8WT1
A8WT0
–
reserved
A6DF1
Area 6
A6DF0
output disable delay time
–
reserved
A6WT2
Area 6 wait control
A6WT1
A6WT0
–
reserved
A5SZ
Areas 5–4 device size selection
A5DF1
Areas 5–4
A5DF0
output disable delay time
–
reserved
A5WT2
Areas 5–4 wait control
A5WT1
A5WT0
EPSON
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Setting
–
1 Used
0 Not used
1 Used
0 Not used
1 8 bits
0 16 bits
A14DF[1:0] Number of cycles
1
1
3.5
1
0
2.5
0
1
1.5
0
0
0.5
–
A14WT[2:0]
Wait cycles
1
1
1
7
1
1
0
6
1
0
1
5
1
0
0
4
0
1
1
3
0
1
0
2
0
0
1
1
0
0
0
0
–
1 Used
0 Not used
1 Used
0 Not used
1 8 bits
0 16 bits
A8DF[1:0] Number of cycles
1
1
3.5
1
0
2.5
0
1
1.5
0
0
0.5
–
A8WT[2:0]
Wait cycles
1
1
1
7
1
1
0
6
1
0
1
5
1
0
0
4
0
1
1
3
0
1
0
2
0
0
1
1
0
0
0
0
–
A6DF[1:0] Number of cycles
1
1
3.5
1
0
2.5
0
1
1.5
0
0
0.5
–
A6WT[2:0]
Wait cycles
1
1
1
7
1
1
0
6
1
0
1
5
1
0
0
4
0
1
1
3
0
1
0
2
0
0
1
1
0
0
0
0
–
1 8 bits
0 16 bits
A5DF[1:0] Number of cycles
1
1
3.5
1
0
2.5
0
1
1.5
0
0
0.5
A5WT[2:0]
Wait cycles
1
1
1
7
1
1
0
6
1
0
1
5
1
0
0
4
0
1
1
3
0
1
0
2
0
0
1
1
0
0
0
0
Init. R/W
Remarks
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
1
R/W
1
–
–
0 when being read.
1
R/W
1
1
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
1
R/W
1
–
–
0 when being read.
1
R/W
1
1
–
–
0 when being read.
1
R/W
1
–
–
0 when being read.
1
R/W
1
1
–
–
0 when being read.
0
R/W
1
R/W
1
–
–
0 when being read.
1
R/W
1
1
B-VI-2-23
A-1
B-VI
SDRAM
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