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Successive transfer mode
The channels for which DMOD in control information is set to "01" operate in successive transfer mode. In
this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The
transfer counter is decremented to "0" by one transfer executed.
The operation of IDMA in successive transfer mode is shown by the flow chart in Figure 3.2.
Calculates address of
control information
control information
Transfers one unit of data
Transfer counter - 1
N
control information
IDMA interrupt processing
(if interrupt is enabled)
Trigger
(1) When a trigger is accepted, the address for control information is calculated from the base address and
channel number.
(2) Control information is read from the calculated address into the internal temporary register.
(3) Data of the size set in the control information is read from the source address.
(4) The read data is written to the destination address.
(5) The address is incremented or decremented and the transfer counter is decremented.
(6) Steps (3) to (5) are repeated until the transfer counter reaches 0.
(7) The modified control information is written to RAM.
(8) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA.
Condition
Transfer counter
Transfer counter = "0", DINTEN = "1":
Transfer counter = "0", DINTEN = "0":
S1C33L03 FUNCTION PART
START
A
Base address + (Channel number
Loads channel
B (3 words)
C (Data read from source of transfer)
D (Data write to destination of transfer)
E
Transfer
counter = 0
Y
Saves channel
F (3 words)
END
A
B1 B2 B3 C1 D1 E1
Figure 3.2 Operation Flow in Successive Transfer Mode
Interrupt factor flag
"0":
Reset ("0")
Not changed ("1")
Reset ("0")
EPSON
V DMA BLOCK: IDMA (Intelligent DMA)
12)
Cn Dn En F1 F2 F3
IDMA request bit
IDMA enable bit
Not changed ("1")
Not changed ("1")
Reset ("0")
Not changed ("1")
Not changed ("1")
Reset ("0")
A-1
B-V
IDMA
B-V-3-9
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