I/O Memory Of Watchdog Timer; Programming Notes - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

I/O Memory of Watchdog Timer

Table 5.1 shows the control bits of the watchdog timer.
Register name Address Bit
Watchdog 0040170 D7
timer write- (B) D6–0
protect register
Watchdog 0040171 D7–2
timer enable (B) D1
register D0
WRWD: EWD write protection (D7) / Watchdog timer write-protect register (0x40170)
Enables writing to the EWD register.
Write "1": Writing enabled
Write "0": Write-protected
Read: Valid
The EWD bit is write-protected to prevent unwanted modifications. Writing to this bit is enabled for only one
writing by setting WRWD to "1". WRWD is reset back to "0" by writing to EWD, so EWD is write-protected
again.
If WRWD is reset to "0" when EWD is write-enabled (WRWD = "1"), EWD becomes write-protected again.
At initial reset, WRWD is set to "0" (write-protected).
EWD: NMI enable (D1) / Watchdog timer enable register (0x40171)
Controls the generation of a nonmaskable interrupt (NMI) by the watchdog timer.
Write "1": NMI is enabled
Write "0": NMI is disabled
Read: Valid
The watchdog timer's interrupt signal is masked by writing "0" to EWD, so a nonmaskable interrupt (NMI) to the
CPU is not generated. If EWD is set to "1", an NMI is generated by the 16-bit programmable timer 0 comparison B
signal.
Writing to EWD is valid only when WRWD = "1".
Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI has
been temporarily disabled, be sure to reset the 16-bit programmable timer 0 before setting the EWD register back
to "1".
At initial reset, EWD is set to "0" (NMI disabled).

Programming Notes

(1) If the watchdog timer's NMI is enabled, the watchdog timer must be reset in the software before the 16-bit
programmable timer 0 outputs the comparison B signal.
(2) Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI
has been temporarily disabled, be sure to reset the 16-bit programmable timer 0 before setting EWD back to
"1".
S1C33L03 FUNCTION PART
Table 5.1 Control Bits of Watchdog Timer
Name Function
WRWD EWD write protection
– –
– –
EWD Watchdog timer enable
– –
EPSON
III PERIPHERAL BLOCK: WATCHDOG TIMER
Setting Init. R/W
1 Write enabled 0 Write-protect 0
– –
– –
1 NMI enabled 0 NMI disabled 0
– –
A-1
Remarks
R/W
– 0 when being read.
– 0 when being read.
R/W
– 0 when being read.
B-III
WDT
B-III-5-3