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•
The writing process continues uninter-
rupted until the controller drops Device
Command Strobe to terminate the opera-
tion.
This drops WX'ite Enable within
the
drive to pX'event the write driver
chain fl:'OlD writing flux transitions on
the pack
e
SERDES and the bit counteX'
aX'e forcibly reset to zeX'o.
Write Compensanon
General
The write compensation circuit converts the
NRZ data from SERDES into MFM data while
compensating for a read condition known as
peak shift.
Peak Shift
Peak shift is an effect that degrades read
accuracy by distorting the waveform.
This
condition exists because no electromechanical
device can be perfect.
In an ideal world, the flux reversal command
by the write toggle would be instantaneous
as shown in the Ideal Recording portion of
Fiqure
3-42.
Current would immediately
switch frOID one polarity to the other.
As
a result, the distance required
to
complete
the magnetic flux reversal on the disk would
be so narrow as to be insignificant; the
readback pulse would then also be extremely
narrow.
To carry the principle one step
further, the heads would be an infinitesimal
distance from the disk surface.
Therefore,
the head gap itself could be" made very small
for two reasons:
•
The magnetic field strength increases
as the head moves closer to the disk.
•
The head gap must
be
wide enough" to
intersect sufficient lines of force
from the magnetic flux field to gener-
ate a Signal.
The weaker the signal,
the wider the gap must be.
Wi th the
substantial flux amplitude gained by
having the head very close to the disk
surface, a very small head gaF can
generate a reliable readback voltage.
But in the real world, it takes time for the
current to reverse; the flux change is not
instantaneous.
Furthermore, heads must fly
a finite distance from the disk.
The great-
er the distance between the head and the
oxide, the wider the head gap must be.
The
resulting readback voltage is more or less
sinusoidal with peaks less easily defined
in time or amplitude.
With modern high frequency recording tech-
niques, adjacent clock/data pulses are close
enough to interact with each other.
This is
3-84
shown in Fiqure 3-43.
Peak shift is the
result of the interaction of the pulses.
Because two pulses tend to have a portion
of their individual Signals superimpose
themselves on each other, the actual read-
back voltage is the algebraic summation of
the pulses.
When all ·l's· or all
·O's·
are being re-
corded,
the
data frequency is constant:
pulses are spaced apart by one cell (155
nanoseconds).
As a result, the pulse spac-
ing causes the overlap errors
to
be equal
and opposite.
The negative-qoing and posi-
tive-qoing erl:'Ors cancel each other.
This
is the ·zero peak shift· condition of the
• ••• 111 ••• • pattern in Figure 3-43.
Peak shift occurs when there is a change in
frequency.
A -011- pattern represents a
frequency increase since there is a delay
of about 1.5 cell between the ·01" and only
1. 0 cell between
the
·11-.
As
a result, the
squeezing of the cells causes the mathema-
tical average (the actual readback voltage)
to shift the apparent peak to the left.
This is early peak shift.
On
the other hand, a
-10-
pattern represents
a frequency decrease since a pulse is not
written at all in the second cell.
In ad-
dition, a ·001- pattern is also a frequency
decrease since there is a
100
cell interval
between the first
two
bits and 1.5 cell
between the last
~.ro
bits
0
The examples listed above examined only two
or three bits without regard to the preced-
ing or subsequent data pattern.
The actual
combinations are somewhat more complex. The
drive logic examines and defines the follow-
ing patterns:
Pattern
011
1000
10
001
Freguency Change
Increasing
Increasing
Decreasing
Decreasing
Any data pattern will have considerable
~
lapping of the data pattern frequency
~ges.
Consider the overlap of these eight bits:
r=Increasin g Frequency
i
~Il
1 0
L
Decreasing
3
Frequency
83318200
A
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