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7M91
Figure 3-32.
Machine Clock Circuit
There are three inputs to the comparator.
One is the normal input from dibits delayed
approximately 1/4 cell and shaped to 30 nsec
(approximate) pulses.
The second input is a
dub-in input.
This is a 30 nsec pulse com-
ing up at the same time as the normal input
but from the clock output.
The third input
is the reset pulse.
It is the normal and
the reset input which provide the basis for
normal comparator operation.
During normal operation, a look-ahead pulse
blocks the dub-in input to the comparator.
This insures that the comparator and there-
fore the clock, tracks with the real input
data from dibits.
However, if dibits are
missing, as they are during the index mark
(for two cells) or during a seek (every
other cell), there must be a pseudo-dibit or
dub-in pulse to keep the clock in phase.
Therefore, the circuit is self-ringing when
data is not present at the input.
A
problem with the self-ringing feature of
the circuit is that, if the first input to
the comparator is not data but a dub-in
pulse, the circuit may not be in synchron-
ization with real daua when it is received.
It would then take some time before synchron-
ization could be attained.
The
5
ms dub-in
inhibit pulse fires to block dub-in pulses
in three situations:
1) when the latch is
cleared by reverse EOT at the end of a first
83318200
A
seek, or 2) and 3) when On Cylinder is re-
ceived after a forward or reverse seek error.
After the heads are loaded, even/odd dibits
are available.
Their nominal frequency is
806 kHz.
The actual frequency is a function
of spindle motor speed.
The
PLL
quickly
synchronizes itself to the actual dibit rate.
This permits the clock to react to variations
in spindle speed between drives.
Signals
derived from this circuit, such as sectors,
are a function of actual spindle speed
rather than functions of an absolute time
base.
FF K35l is connected as a divide-by-two
circuit.
This circuit arrangement permits
the PLL feedback to be a function of nega-
tive-going edges of the
PLL
output.
There-
fore,
PLL
unsymetrical outputs are ignored
and the basic frequency is the controlling
factor.
The
PLL
output frequency is nomi-
nally 1.612
MHz.
WRITE CLOCK
Write Clock is derived directly from the
basic 806 kHz clock.
Three phase lock os-
cillators and a divide by two flip-flop
generate the basic 6.44
MHz
clock signal
to the write circuitry.
The frequency is
gradually increased to permit the generation
of stable pulses.
3-71
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