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Model 11869A
NTEGRATED CIRCUIT SYMBOLOGY
Schmitt Trigger:
The gate of the Schmitt
Trigger switches at different points for
positive-and negative-going signals. The
difference between the positive and neg¬
ative thresholds is defined as hysteresis
voltage.
Counter: Binary-weighted registers count
on the falling edge of each clock pulse.
Active (high) R clears all registers.
3-State Buffer: Three States:
Enable (EM) Input low: High impedence
output.
Enable input high: Output = 0 or
Output = 1
Data Flip-Flop: Set (S) and Reset (R) are
asynchronous controls. Active S sets the
noninverting output high and the inverting
output (o—) low; active R resets both
outputs. When S and R are both inactive,
the outputs remain latched in the last
state. An active clock {-§> } enables the
D input, at which time the noninverting
output = D, and the inverting output
= D.
Control Block: All controlling inputs (gates,
clocks, inhibits, etc.) connect to the con¬
trol block.
Elements: Can be one or more of any logic
function (flip-flop, counter, gate, RAM,
etc.). Data inputs are on the left side of
element, data outputs on the right.
: D9
i
: DIG
; Dll (MSB)
I_
Digital to Analog Converter (DAC):
Provides a scaled current output (11),
the product of VRE F and the fractional
binary input:
D112-1 + O102~2 + Dg2-3 + ... DQ2 "12
The product of VREF and complement of
the binary input appears at l2.
Decoder: The logic states of the three sel¬
ect lines A, B, and C, and the three enable
inputs (EM), determine which one of the
eight outputs wili be decoded. The sel¬
ected output will be low, while all others
are high.
Analog Switch: Control lines 1 and 2
decode to select one of four inputs. G1,
high=enable.
Random-Access Memory (RAM):
Binary addresses (AO to A9) access one of
1024 registers in RAM. When G1 is high,
bits appearing at DO to D3 will be written
to the addressed location (AO to A9).
When G2 is tow, bits appearing at DO to
03 have been accessed from the addressed
location.
8-4
Figure 8-1. Schematic Diagram Notes (2 of 3)
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