Table of Contents
Advertisement
Philips Semiconductors
ARM-based Microcontroller
REGISTER DESCRIPTION
The VIC implements the registers shown in Table 40. More detailed descriptions follow.
Table 40: VIC Register Map
Name
IRQ Status Register. This register reads out the state of those interrupt
VICIRQStatus
requests that are enabled and classified as IRQ.
FIQ Status Requests. This register reads out the state of those interrupt
VICFIQStatus
requests that are enabled and classified as FIQ.
Raw Interrupt Status Register. This register reads out the state of the 32
VICRawIntr
interrupt requests / software interrupts, regardless of enabling or
classification.
Interrupt Select Register. This register classifies each of the 32 interrupt
VICIntSelect
requests as contributing to FIQ or IRQ.
Interrupt Enable Register. This register controls which of the 32 interrupt
VICIntEnable
requests and software interrupts are enabled to contribute to FIQ or
IRQ.
Interrupt Enable Clear Register. This register allows software to clear
VICIntEnClr
one or more bits in the Interrupt Enable register.
Software Interrupt Register. The contents of this register are ORed with
VICSoftInt
the 32 interrupt requests from various peripheral functions.
Software Interrupt Clear Register. This register allows software to clear
VICSoftIntClear
one or more bits in the Software Interrupt register.
Protection enable register. This register allows limiting access to the VIC
VICProtection
registers by software running in privileged mode.
Vector Address Register. When an IRQ interrupt occurs, the IRQ service
VICVectAddr
routine can read this register and jump to the value read.
Default Vector Address Register. This register holds the address of the
VICDefVectAddr
Interrupt Service routine (ISR) for non-vectored IRQs.
Vector address 0 register. Vector Address Registers 0-15 hold the
VICVectAddr0
addresses of the Interrupt Service routines (ISRs) for the 16 vectored
IRQ slots.
VICVectAddr1
Vector address 1 register
VICVectAddr2
Vector address 2 register
VICVectAddr3
Vector address 3 register
VICVectAddr4
Vector address 4 register
VICVectAddr5
Vector address 5 register
VICVectAddr6
Vector address 6 register
VICVectAddr7
Vector address 7 register
VICVectAddr8
Vector address 8 register
VICVectAddr9
Vector address 9 register
Vectored Interrupt Controller (VIC)
Description
97
Preliminary User Manual
LPC2119/2129/2194/2292/2294
Reset
Access
Value*
RO
0
RO
0
RO
0
R/W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Address
0xFFFF F000
0xFFFF F004
0xFFFF F008
0xFFFF F00C
0xFFFF F010
0xFFFF F014
0xFFFF F018
0xFFFF F01C
0xFFFF F020
0xFFFF F030
0xFFFF F034
0xFFFF F100
0xFFFF F104
0xFFFF F108
0xFFFF F10C
0xFFFF F110
0xFFFF F114
0xFFFF F118
0xFFFF F11C
0xFFFF F120
0xFFFF F124
May 03, 2004
Advertisement
Table of Contents
