Spurious Interrupts - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller

SPURIOUS INTERRUPTS

Spurious interrupts are possible to occur in the ARM7TDMI based microcontroller such as the LPC2119/2129/2194/2292/2294
due to the asynchronous interrupt handling. The asynchronous character of the interrupt processing has its roots in the interaction
of the core and the VIC. If the VIC state is changed between the moments when the core detects an interrupt and the core actually
processes an interrupt, problems may be generated.
Real-life application may experience following scenario:
1) VIC decides there is an IRQ interrupt and sends the IRQ signal to the core.
2) Core latches the IRQ state.
3) Processing continues for a few cycles due to pipelining.
4) Core loads IRQ address from VIC.
Furthermore, It is possible that the VIC state has changed during the step 3. For example, VIC was modified so that the interrupt
that triggered the sequence starting with step 1) is no longer pending -interrupt got disabled in the executed code. In this case,
the VIC will not be able to clearly identify the interrupt that generated the interrupt request, and as a result the VIC will return the
default interrupt VicDefVectAddr (0xFFFF F034).
This potentialy disastrous chain of events can be prevented in two ways:
1. Application code should be set up in a way to prevent the spurious interrupts to ever happen. Simple guarding of changes to
the VIC may not not be enough, since for example glitches on level sensitive interrupts can also cause spurious interrupts.
2. VIC default handler should be set up and tested properly.
Details and Case Studies on Spurious Interrupts
This chapter contains details that can be obtained from the official ARM website (http://www.arm.com), FAQ section under the
"Technical Support" link: http://www.arm.com/support/faqip/3677.html.
What happens if an interrupt occurs as it is being disabled?
Applies to: ARM7TDMI
If an interrupt is received by the core during execution of an instruction that disables interrupts, the ARM7 family will still take the
interrupt. This occurs for both IRQ and FIQ interrupts.
For example, consider the follow instruction sequence:
MRS r0, cpsr
ORR r0, r0, #I_Bit:OR:F_Bit
MSR cpsr_c, r0
If an IRQ interrupt is received during execution of the MSR instruction, then the behavior will be as follows:
• The IRQ interrupt is latched
• The MSR cpsr, r0 executes to completion setting both the I bit and the F bit in the CPSR
• The IRQ interrupt is taken because the core was committed to taking the interrupt exception before the I bit was set in the
CPSR.
• The CPSR (with the I bit and F bit set) is moved to the SPSR_irq
Vectored Interrupt Controller (VIC)
;disable IRQ and FIQ interrupts
106
Preliminary User Manual
LPC2119/2129/2194/2292/2294
May 03, 2004