Cgfcen] (Clock Supply And Stop Register For Fc); Cgspclken] (Clock Supply And Stop Register For Adc And Debug Circuit) - Toshiba TXZ+ TMPM4MNFYAFG Reference Manual

[CGFCEN] (Clock supply and stop register for fc)

Bit Bit Symbol
31:29 -
28 FCIPEN28
27 FCIPEN27
26 FCIPEN26
25:24 -
23 FCIPEN23
22:0 -
Note: Even if the initial value of the register is set to stop of the clock, the clock is supplied during the reset.

[CGSPCLKEN] (Clock supply and stop register for ADC and Debug circuit)

Bit Bit Symbol
31:20 -
19 -
18 ADCKEN2
17 ADCKEN1
16 ADCKEN0
15:1 -
0 TRCKEN
Note1: Even if the initial value of the register is set to stop of the clock, the clock is supplied during the reset.
Note2: When setting this bit to "0" (clock stop), please make sure that AD conversion is stopped.
After reset Type
0 R Read as "0"
Clock enable of DNF Unit C (INT21)
0 R/W
0: Clock stop
1: Clock supply
Clock enable of DNF Unit B (INT08b to 18)
0 R/W
0: Clock stop
1: Clock supply
Clock enable of DNF Unit A (INT00 to 08a,11b)
0 R/W
0: Clock stop
1: Clock supply
0 R Read as "0"
Clock enable of OFD detection target clock 1 (fc)
0 R/W
0: Clock stop
1: Clock supply
0 R Read as "0"
After reset Type
0 R Read as "0"
0 R/W Write as "0"
Enable the clock for ADC unit C (Note2)
0 R/W
0: Clock stop
1: Clock supply
Enable the clock for ADC unit B (Note2)
0 R/W
0: Clock stop
1: Clock supply
Enable the clock for ADC unit A (Note2)
0 R/W
0: Clock stop
1: Clock supply
0 R Read as "0"
Enable the Clock for the Trace function of Debug circuit (Trace or
SWV).
0 R/W
0: Clock stop
1: Clock supply
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TMPM4M Group(1)
Clock Control and Operation Mode
Function
Function
TXZ+ Family
2022-06-24
Rev. 1.1